From 24ff30a814dc44f3680697324dd9443863c7f323 Mon Sep 17 00:00:00 2001 From: Phani Kumar Uppalapati Date: Mon, 30 Jan 2017 17:47:26 -0800 Subject: [PATCH] ASoC: wcd934x: Update master clock sequence for wcd934x codec Update master clock sequence for wcd934x codec to avoid mute when codec core goes in and comes out of power collapse. Change-Id: Id85c8437bf99d1b0bd1ab8f7e8a7f3fcf7e93856 Signed-off-by: Phani Kumar Uppalapati --- sound/soc/codecs/wcd934x/wcd934x.c | 2 +- sound/soc/codecs/wcd9xxx-resmgr-v2.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/sound/soc/codecs/wcd934x/wcd934x.c b/sound/soc/codecs/wcd934x/wcd934x.c index 0030b1fcf773..fbd40fba8586 100644 --- a/sound/soc/codecs/wcd934x/wcd934x.c +++ b/sound/soc/codecs/wcd934x/wcd934x.c @@ -7859,9 +7859,9 @@ static int tavil_dig_core_remove_power_collapse(struct snd_soc_codec *codec) snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); - snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x00); snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x02); + snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); wcd9xxx_set_power_state(tavil->wcd9xxx, WCD_REGION_POWER_COLLAPSE_REMOVE, diff --git a/sound/soc/codecs/wcd9xxx-resmgr-v2.c b/sound/soc/codecs/wcd9xxx-resmgr-v2.c index 71edded182e0..2229109aec3d 100644 --- a/sound/soc/codecs/wcd9xxx-resmgr-v2.c +++ b/sound/soc/codecs/wcd9xxx-resmgr-v2.c @@ -247,15 +247,15 @@ static int wcd_resmgr_enable_clk_mclk(struct wcd9xxx_resmgr_v2 *resmgr) * to CLK_SYS_MCLK_PRG */ wcd_resmgr_codec_reg_update_bits(resmgr, - WCD934X_CLK_SYS_MCLK_PRG, 0x91, 0x91); + WCD934X_CLK_SYS_MCLK_PRG, 0x80, 0x80); + wcd_resmgr_codec_reg_update_bits(resmgr, + WCD934X_CLK_SYS_MCLK_PRG, 0x30, 0x10); wcd_resmgr_codec_reg_update_bits(resmgr, WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x00); wcd_resmgr_codec_reg_update_bits(resmgr, - WCD934X_CLK_SYS_INT_CLK_TEST2, 0x04, - 0x04); + WCD934X_CLK_SYS_MCLK_PRG, 0x01, 0x01); wcd_resmgr_codec_reg_update_bits(resmgr, - WCD934X_CLK_SYS_INT_CLK_TEST2, 0x04, - 0x00); + WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x00); wcd_resmgr_codec_reg_update_bits(resmgr, WCD93XX_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x01, 0x01); @@ -311,6 +311,9 @@ static int wcd_resmgr_disable_clk_mclk(struct wcd9xxx_resmgr_v2 *resmgr) 0x08, 0x08); wcd_resmgr_codec_reg_update_bits(resmgr, WCD934X_CLK_SYS_MCLK_PRG, 0x02, 0x02); + /* Disable clock buffer */ + wcd_resmgr_codec_reg_update_bits(resmgr, + WCD934X_CLK_SYS_MCLK_PRG, 0x80, 0x00); resmgr->clk_type = WCD_CLK_RCO; } else { wcd_resmgr_codec_reg_update_bits(resmgr,