clk: msm: mdss: fix 32 bit compilation issues
Fix 32bit compilation issues in DSI and HDMI pll driver. Also avoid udelay of more than 2ms as it gives a fake __bad_udelay reference at link-time on 32bit build. Change-Id: I2681c0fb2a7d69ee8a3f9f6d18164c3cb482d2f7 Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org> Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
This commit is contained in:
Vishnuvardhan Prodduturi
David Keitel
parent
d2cb90a1d5
commit
45c2d389ad
3 changed files with 81 additions and 65 deletions
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@ -414,7 +414,7 @@ static void pll_8996_ssc_calc(struct mdss_pll_resources *pll,
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pll->vco_current_rate, pll->vco_ref_clk_rate);
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ssc_period = pdb->in.ssc_freq / 500;
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period = pll->vco_ref_clk_rate / 1000;
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period = (unsigned long)pll->vco_ref_clk_rate / 1000;
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ssc_period = CEIL(period, ssc_period);
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ssc_period -= 1;
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pdb->out.ssc_period = ssc_period;
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@ -477,7 +477,7 @@ static void pll_8996_dec_frac_calc(struct mdss_pll_resources *pll,
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pll_comp_val = duration * dec_start_multiple;
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pll_comp_val = div_s64(pll_comp_val, multiplier);
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pll_comp_val /= 10;
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do_div(pll_comp_val, 10);
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pout->plllock_cmp = (u32)pll_comp_val;
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@ -492,11 +492,11 @@ static u32 pll_8996_kvco_slop(u32 vrate)
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{
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u32 slop = 0;
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if (vrate > 1300000000 && vrate <= 1800000000)
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if (vrate > 1300000000UL && vrate <= 1800000000UL)
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slop = 600;
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else if (vrate > 1800000000 && vrate < 2300000000)
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else if (vrate > 1800000000UL && vrate < 2300000000UL)
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slop = 400;
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else if (vrate > 2300000000 && vrate < 2600000000)
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else if (vrate > 2300000000UL && vrate < 2600000000UL)
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slop = 280;
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return slop;
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@ -511,25 +511,25 @@ static void pll_8996_calc_vco_count(struct dsi_pll_db *pdb,
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u32 cnt;
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data = fref * pin->vco_measure_time;
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data /= 1000000;
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do_div(data, 1000000);
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data &= 0x03ff; /* 10 bits */
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data -= 2;
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pout->pll_vco_div_ref = data;
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data = vco_clk_rate / 1000000; /* unit is Mhz */
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data = (unsigned long)vco_clk_rate / 1000000; /* unit is Mhz */
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data *= pin->vco_measure_time;
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data /= 10;
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do_div(data, 10);
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pout->pll_vco_count = data; /* reg: 0x0474, 0x0478 */
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data = fref * pin->kvco_measure_time;
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data /= 1000000;
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do_div(data, 1000000);
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data &= 0x03ff; /* 10 bits */
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data -= 1;
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pout->pll_kvco_div_ref = data;
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cnt = pll_8996_kvco_slop(vco_clk_rate);
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cnt *= 2;
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cnt /= 100;
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do_div(cnt, 100);
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cnt *= pin->kvco_measure_time;
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pout->pll_kvco_count = cnt;
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@ -83,9 +83,9 @@ static struct clk_div_ops shadow_n2_div_ops = {
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};
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static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
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.ref_clk_rate = 19200000,
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.min_rate = 1300000000,
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.max_rate = 2600000000,
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.ref_clk_rate = 19200000UL,
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.min_rate = 1300000000UL,
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.max_rate = 2600000000UL,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
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.c = {
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@ -107,9 +107,9 @@ static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
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};
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static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
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.ref_clk_rate = 19200000,
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.min_rate = 1300000000,
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.max_rate = 2600000000,
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.ref_clk_rate = 19200000UL,
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.min_rate = 1300000000UL,
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.max_rate = 2600000000UL,
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.pll_en_seq_cnt = 1,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
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.c = {
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@ -25,8 +25,8 @@
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/* CONSTANTS */
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#define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10
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#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000
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#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000
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#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000UL
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#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000UL
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#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 750000000
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#define HDMI_CLKS_PLL_DIVSEL 0
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#define HDMI_CORECLK_DIV 5
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@ -39,13 +39,13 @@
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#define HDMI_VCO_MAX_FREQ 12000000000
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#define HDMI_VCO_MIN_FREQ 8000000000
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#define HDMI_2400MHZ_BIT_CLK_HZ 2400000000
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#define HDMI_2250MHZ_BIT_CLK_HZ 2250000000
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#define HDMI_2000MHZ_BIT_CLK_HZ 2000000000
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#define HDMI_1700MHZ_BIT_CLK_HZ 1700000000
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#define HDMI_1200MHZ_BIT_CLK_HZ 1200000000
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#define HDMI_1334MHZ_BIT_CLK_HZ 1334000000
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#define HDMI_1000MHZ_BIT_CLK_HZ 1000000000
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#define HDMI_2400MHZ_BIT_CLK_HZ 2400000000UL
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#define HDMI_2250MHZ_BIT_CLK_HZ 2250000000UL
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#define HDMI_2000MHZ_BIT_CLK_HZ 2000000000UL
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#define HDMI_1700MHZ_BIT_CLK_HZ 1700000000UL
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#define HDMI_1200MHZ_BIT_CLK_HZ 1200000000UL
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#define HDMI_1334MHZ_BIT_CLK_HZ 1334000000UL
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#define HDMI_1000MHZ_BIT_CLK_HZ 1000000000UL
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#define HDMI_850MHZ_BIT_CLK_HZ 850000000
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#define HDMI_667MHZ_BIT_CLK_HZ 667000000
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#define HDMI_600MHZ_BIT_CLK_HZ 600000000
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@ -318,8 +318,8 @@
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#define HDMI_PHY_PHY_REVISION_ID2 (0xC0)
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#define HDMI_PHY_PHY_REVISION_ID3 (0xC4)
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#define HDMI_PLL_POLL_MAX_READS 2500
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#define HDMI_PLL_POLL_TIMEOUT_US 150000
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#define HDMI_PLL_POLL_MAX_READS 100
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#define HDMI_PLL_POLL_TIMEOUT_US 1500
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enum hdmi_pll_freqs {
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HDMI_PCLK_25200_KHZ,
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@ -490,13 +490,13 @@ static inline u64 hdmi_8996_get_coreclk_div_ratio(u64 clks_pll_divsel,
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static inline u64 hdmi_8996_v1_get_tx_band(u64 bclk)
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{
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if (bclk >= 2400000000)
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if (bclk >= 2400000000UL)
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return 0;
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if (bclk >= 1200000000)
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if (bclk >= 1200000000UL)
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return 1;
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if (bclk >= 600000000)
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if (bclk >= 600000000UL)
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return 2;
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if (bclk >= 300000000)
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if (bclk >= 300000000UL)
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return 3;
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return HDMI_64B_ERR_VAL;
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@ -518,13 +518,13 @@ static inline u64 hdmi_8996_v2_get_tx_band(u64 bclk, u64 vco_range)
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static inline u64 hdmi_8996_v1_get_hsclk(u64 fdata)
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{
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if (fdata >= 9600000000)
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if (fdata >= 9600000000UL)
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return 0;
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else if (fdata >= 4800000000)
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else if (fdata >= 4800000000UL)
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return 1;
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else if (fdata >= 3200000000)
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else if (fdata >= 3200000000UL)
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return 2;
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else if (fdata >= 2400000000)
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else if (fdata >= 2400000000UL)
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return 3;
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return HDMI_64B_ERR_VAL;
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@ -1855,9 +1855,10 @@ static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk, u32 ver)
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static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io)
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{
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u32 status;
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u32 status = 0;
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int phy_ready = 0;
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int rc;
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u32 read_count = 0;
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rc = mdss_pll_resource_enable(io, true);
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if (rc) {
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@ -1868,16 +1869,20 @@ static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io)
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DEV_DBG("%s: Waiting for PHY Ready\n", __func__);
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/* Poll for PHY read status */
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if (!readl_poll_timeout_atomic(
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(io->phy_base + HDMI_PHY_STATUS),
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status, ((status & BIT(0)) == 1),
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HDMI_PLL_POLL_MAX_READS,
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HDMI_PLL_POLL_TIMEOUT_US)) {
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DEV_DBG("%s: PHY READY\n", __func__);
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phy_ready = 1;
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} else {
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DEV_ERR("%s: PHY READY TIMEOUT\n", __func__);
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while (read_count < HDMI_PLL_POLL_MAX_READS) {
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status = MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS);
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if ((status & BIT(0)) == 1) {
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phy_ready = 1;
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DEV_DBG("%s: PHY READY\n", __func__);
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break;
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}
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udelay(HDMI_PLL_POLL_TIMEOUT_US);
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read_count++;
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}
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if (read_count == HDMI_PLL_POLL_MAX_READS) {
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phy_ready = 0;
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DEV_ERR("%s: PHY READY TIMEOUT\n", __func__);
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}
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mdss_pll_resource_enable(io, false);
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@ -1890,6 +1895,7 @@ static int hdmi_8996_pll_lock_status(struct mdss_pll_resources *io)
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u32 status;
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int pll_locked = 0;
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int rc;
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u32 read_count = 0;
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rc = mdss_pll_resource_enable(io, true);
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if (rc) {
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@ -1899,16 +1905,21 @@ static int hdmi_8996_pll_lock_status(struct mdss_pll_resources *io)
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DEV_DBG("%s: Waiting for PLL lock\n", __func__);
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if (!readl_poll_timeout_atomic(
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(io->pll_base + QSERDES_COM_C_READY_STATUS),
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status, ((status & BIT(0)) == 1),
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HDMI_PLL_POLL_MAX_READS,
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HDMI_PLL_POLL_TIMEOUT_US)) {
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DEV_DBG("%s: C READY\n", __func__);
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pll_locked = 1;
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} else {
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DEV_ERR("%s: C READY TIMEOUT\n", __func__);
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while (read_count < HDMI_PLL_POLL_MAX_READS) {
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status = MDSS_PLL_REG_R(io->pll_base,
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QSERDES_COM_C_READY_STATUS);
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if ((status & BIT(0)) == 1) {
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pll_locked = 1;
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DEV_DBG("%s: C READY\n", __func__);
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break;
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}
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udelay(HDMI_PLL_POLL_TIMEOUT_US);
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read_count++;
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}
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if (read_count == HDMI_PLL_POLL_MAX_READS) {
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pll_locked = 0;
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DEV_ERR("%s: C READY TIMEOUT\n", __func__);
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}
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mdss_pll_resource_enable(io, false);
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@ -2062,20 +2073,25 @@ static int hdmi_8996_v2_perform_sw_calibration(struct clk *c)
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struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
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struct mdss_pll_resources *io = vco->priv;
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u32 vco_code1, vco_code2, integral_loop, ready_poll;
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u32 read_count = 0;
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if (!readl_poll_timeout_atomic(
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(io->pll_base + QSERDES_COM_C_READY_STATUS),
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ready_poll, ((ready_poll & BIT(0)) == 1),
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HDMI_PLL_POLL_MAX_READS,
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HDMI_PLL_POLL_TIMEOUT_US << 1)) {
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DEV_DBG("%s: C READY\n", __func__);
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ready_poll = 1;
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} else {
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DEV_DBG("%s: C READY TIMEOUT, TRYING SW CALIBRATION\n",
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__func__);
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ready_poll = 0;
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while (read_count < (HDMI_PLL_POLL_MAX_READS << 1)) {
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ready_poll = MDSS_PLL_REG_R(io->pll_base,
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QSERDES_COM_C_READY_STATUS);
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if ((ready_poll & BIT(0)) == 1) {
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ready_poll = 1;
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DEV_DBG("%s: C READY\n", __func__);
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break;
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}
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udelay(HDMI_PLL_POLL_TIMEOUT_US);
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read_count++;
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}
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if (read_count == (HDMI_PLL_POLL_MAX_READS << 1)) {
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ready_poll = 0;
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DEV_DBG("%s: C READY TIMEOUT, TRYING SW CALIBRATION\n",
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__func__);
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}
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vco_code1 = MDSS_PLL_REG_R(io->pll_base,
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QSERDES_COM_PLLCAL_CODE1_STATUS);
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