evie/android_kernel_oneplus_msm8998
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clk: msm: mdss: fix 32 bit compilation issues

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Fix 32bit compilation issues in DSI and HDMI pll driver.
Also avoid udelay of more than 2ms as it gives a fake
__bad_udelay reference at link-time on 32bit build.

Change-Id: I2681c0fb2a7d69ee8a3f9f6d18164c3cb482d2f7
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
This commit is contained in:
Vishnuvardhan Prodduturi 2015-11-13 14:35:40 +05:30 • committed by David Keitel
parent d2cb90a1d5
commit 45c2d389ad
3 changed files with 81 additions and 65 deletions
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20
drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c
View file

@ -414,7 +414,7 @@ static void pll_8996_ssc_calc(struct mdss_pll_resources *pll,
pll->vco_current_rate, pll->vco_ref_clk_rate); pll->vco_current_rate, pll->vco_ref_clk_rate);
ssc_period = pdb->in.ssc_freq / 500; ssc_period = pdb->in.ssc_freq / 500;
period = pll->vco_ref_clk_rate / 1000; period = (unsigned long)pll->vco_ref_clk_rate / 1000;
ssc_period = CEIL(period, ssc_period); ssc_period = CEIL(period, ssc_period);
ssc_period -= 1; ssc_period -= 1;
pdb->out.ssc_period = ssc_period; pdb->out.ssc_period = ssc_period;
@ -477,7 +477,7 @@ static void pll_8996_dec_frac_calc(struct mdss_pll_resources *pll,
pll_comp_val = duration * dec_start_multiple; pll_comp_val = duration * dec_start_multiple;
pll_comp_val = div_s64(pll_comp_val, multiplier); pll_comp_val = div_s64(pll_comp_val, multiplier);
pll_comp_val /= 10; do_div(pll_comp_val, 10);
pout->plllock_cmp = (u32)pll_comp_val; pout->plllock_cmp = (u32)pll_comp_val;
@ -492,11 +492,11 @@ static u32 pll_8996_kvco_slop(u32 vrate)
{ {
u32 slop = 0; u32 slop = 0;
if (vrate > 1300000000 && vrate <= 1800000000) if (vrate > 1300000000UL && vrate <= 1800000000UL)
slop = 600; slop = 600;
else if (vrate > 1800000000 && vrate < 2300000000) else if (vrate > 1800000000UL && vrate < 2300000000UL)
slop = 400; slop = 400;
else if (vrate > 2300000000 && vrate < 2600000000) else if (vrate > 2300000000UL && vrate < 2600000000UL)
slop = 280; slop = 280;
return slop; return slop;
@ -511,25 +511,25 @@ static void pll_8996_calc_vco_count(struct dsi_pll_db *pdb,
u32 cnt; u32 cnt;
data = fref * pin->vco_measure_time; data = fref * pin->vco_measure_time;
data /= 1000000; do_div(data, 1000000);
data &= 0x03ff; /* 10 bits */ data &= 0x03ff; /* 10 bits */
data -= 2; data -= 2;
pout->pll_vco_div_ref = data; pout->pll_vco_div_ref = data;
data = vco_clk_rate / 1000000; /* unit is Mhz */ data = (unsigned long)vco_clk_rate / 1000000; /* unit is Mhz */
data *= pin->vco_measure_time; data *= pin->vco_measure_time;
data /= 10; do_div(data, 10);
pout->pll_vco_count = data; /* reg: 0x0474, 0x0478 */ pout->pll_vco_count = data; /* reg: 0x0474, 0x0478 */
data = fref * pin->kvco_measure_time; data = fref * pin->kvco_measure_time;
data /= 1000000; do_div(data, 1000000);
data &= 0x03ff; /* 10 bits */ data &= 0x03ff; /* 10 bits */
data -= 1; data -= 1;
pout->pll_kvco_div_ref = data; pout->pll_kvco_div_ref = data;
cnt = pll_8996_kvco_slop(vco_clk_rate); cnt = pll_8996_kvco_slop(vco_clk_rate);
cnt *= 2; cnt *= 2;
cnt /= 100; do_div(cnt, 100);
cnt *= pin->kvco_measure_time; cnt *= pin->kvco_measure_time;
pout->pll_kvco_count = cnt; pout->pll_kvco_count = cnt;

12
drivers/clk/msm/mdss/mdss-dsi-pll-8996.c
View file

@ -83,9 +83,9 @@ static struct clk_div_ops shadow_n2_div_ops = {
}; };
static struct dsi_pll_vco_clk dsi0pll_vco_clk = { static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
.ref_clk_rate = 19200000, .ref_clk_rate = 19200000UL,
.min_rate = 1300000000, .min_rate = 1300000000UL,
.max_rate = 2600000000, .max_rate = 2600000000UL,
.pll_en_seq_cnt = 1, .pll_en_seq_cnt = 1,
.pll_enable_seqs[0] = dsi_pll_enable_seq_8996, .pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
.c = { .c = {
@ -107,9 +107,9 @@ static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
}; };
static struct dsi_pll_vco_clk dsi1pll_vco_clk = { static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
.ref_clk_rate = 19200000, .ref_clk_rate = 19200000UL,
.min_rate = 1300000000, .min_rate = 1300000000UL,
.max_rate = 2600000000, .max_rate = 2600000000UL,
.pll_en_seq_cnt = 1, .pll_en_seq_cnt = 1,
.pll_enable_seqs[0] = dsi_pll_enable_seq_8996, .pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
.c = { .c = {

108
drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c
View file

@ -25,8 +25,8 @@
/* CONSTANTS */ /* CONSTANTS */
#define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10 #define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10
#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000 #define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000UL
#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000 #define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000UL
#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 750000000 #define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 750000000
#define HDMI_CLKS_PLL_DIVSEL 0 #define HDMI_CLKS_PLL_DIVSEL 0
#define HDMI_CORECLK_DIV 5 #define HDMI_CORECLK_DIV 5
@ -39,13 +39,13 @@
#define HDMI_VCO_MAX_FREQ 12000000000 #define HDMI_VCO_MAX_FREQ 12000000000
#define HDMI_VCO_MIN_FREQ 8000000000 #define HDMI_VCO_MIN_FREQ 8000000000
#define HDMI_2400MHZ_BIT_CLK_HZ 2400000000 #define HDMI_2400MHZ_BIT_CLK_HZ 2400000000UL
#define HDMI_2250MHZ_BIT_CLK_HZ 2250000000 #define HDMI_2250MHZ_BIT_CLK_HZ 2250000000UL
#define HDMI_2000MHZ_BIT_CLK_HZ 2000000000 #define HDMI_2000MHZ_BIT_CLK_HZ 2000000000UL
#define HDMI_1700MHZ_BIT_CLK_HZ 1700000000 #define HDMI_1700MHZ_BIT_CLK_HZ 1700000000UL
#define HDMI_1200MHZ_BIT_CLK_HZ 1200000000 #define HDMI_1200MHZ_BIT_CLK_HZ 1200000000UL
#define HDMI_1334MHZ_BIT_CLK_HZ 1334000000 #define HDMI_1334MHZ_BIT_CLK_HZ 1334000000UL
#define HDMI_1000MHZ_BIT_CLK_HZ 1000000000 #define HDMI_1000MHZ_BIT_CLK_HZ 1000000000UL
#define HDMI_850MHZ_BIT_CLK_HZ 850000000 #define HDMI_850MHZ_BIT_CLK_HZ 850000000
#define HDMI_667MHZ_BIT_CLK_HZ 667000000 #define HDMI_667MHZ_BIT_CLK_HZ 667000000
#define HDMI_600MHZ_BIT_CLK_HZ 600000000 #define HDMI_600MHZ_BIT_CLK_HZ 600000000
@ -318,8 +318,8 @@
#define HDMI_PHY_PHY_REVISION_ID2 (0xC0) #define HDMI_PHY_PHY_REVISION_ID2 (0xC0)
#define HDMI_PHY_PHY_REVISION_ID3 (0xC4) #define HDMI_PHY_PHY_REVISION_ID3 (0xC4)
#define HDMI_PLL_POLL_MAX_READS 2500 #define HDMI_PLL_POLL_MAX_READS 100
#define HDMI_PLL_POLL_TIMEOUT_US 150000 #define HDMI_PLL_POLL_TIMEOUT_US 1500
enum hdmi_pll_freqs { enum hdmi_pll_freqs {
HDMI_PCLK_25200_KHZ, HDMI_PCLK_25200_KHZ,
@ -490,13 +490,13 @@ static inline u64 hdmi_8996_get_coreclk_div_ratio(u64 clks_pll_divsel,
static inline u64 hdmi_8996_v1_get_tx_band(u64 bclk) static inline u64 hdmi_8996_v1_get_tx_band(u64 bclk)
{ {
if (bclk >= 2400000000) if (bclk >= 2400000000UL)
return 0; return 0;
if (bclk >= 1200000000) if (bclk >= 1200000000UL)
return 1; return 1;
if (bclk >= 600000000) if (bclk >= 600000000UL)
return 2; return 2;
if (bclk >= 300000000) if (bclk >= 300000000UL)
return 3; return 3;
return HDMI_64B_ERR_VAL; return HDMI_64B_ERR_VAL;
@ -518,13 +518,13 @@ static inline u64 hdmi_8996_v2_get_tx_band(u64 bclk, u64 vco_range)
static inline u64 hdmi_8996_v1_get_hsclk(u64 fdata) static inline u64 hdmi_8996_v1_get_hsclk(u64 fdata)
{ {
if (fdata >= 9600000000) if (fdata >= 9600000000UL)
return 0; return 0;
else if (fdata >= 4800000000) else if (fdata >= 4800000000UL)
return 1; return 1;
else if (fdata >= 3200000000) else if (fdata >= 3200000000UL)
return 2; return 2;
else if (fdata >= 2400000000) else if (fdata >= 2400000000UL)
return 3; return 3;
return HDMI_64B_ERR_VAL; return HDMI_64B_ERR_VAL;
@ -1855,9 +1855,10 @@ static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk, u32 ver)
static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io) static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io)
{ {
u32 status; u32 status = 0;
int phy_ready = 0; int phy_ready = 0;
int rc; int rc;
u32 read_count = 0;
rc = mdss_pll_resource_enable(io, true); rc = mdss_pll_resource_enable(io, true);
if (rc) { if (rc) {
@ -1868,16 +1869,20 @@ static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io)
DEV_DBG("%s: Waiting for PHY Ready\n", __func__); DEV_DBG("%s: Waiting for PHY Ready\n", __func__);
/* Poll for PHY read status */ /* Poll for PHY read status */
if (!readl_poll_timeout_atomic( while (read_count < HDMI_PLL_POLL_MAX_READS) {
(io->phy_base + HDMI_PHY_STATUS), status = MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS);
status, ((status & BIT(0)) == 1), if ((status & BIT(0)) == 1) {
HDMI_PLL_POLL_MAX_READS,
HDMI_PLL_POLL_TIMEOUT_US)) {
DEV_DBG("%s: PHY READY\n", __func__);
phy_ready = 1; phy_ready = 1;
} else { DEV_DBG("%s: PHY READY\n", __func__);
DEV_ERR("%s: PHY READY TIMEOUT\n", __func__); break;
}
udelay(HDMI_PLL_POLL_TIMEOUT_US);
read_count++;
}
if (read_count == HDMI_PLL_POLL_MAX_READS) {
phy_ready = 0; phy_ready = 0;
DEV_ERR("%s: PHY READY TIMEOUT\n", __func__);
} }
mdss_pll_resource_enable(io, false); mdss_pll_resource_enable(io, false);
@ -1890,6 +1895,7 @@ static int hdmi_8996_pll_lock_status(struct mdss_pll_resources *io)
u32 status; u32 status;
int pll_locked = 0; int pll_locked = 0;
int rc; int rc;
u32 read_count = 0;
rc = mdss_pll_resource_enable(io, true); rc = mdss_pll_resource_enable(io, true);
if (rc) { if (rc) {
@ -1899,16 +1905,21 @@ static int hdmi_8996_pll_lock_status(struct mdss_pll_resources *io)
DEV_DBG("%s: Waiting for PLL lock\n", __func__); DEV_DBG("%s: Waiting for PLL lock\n", __func__);
if (!readl_poll_timeout_atomic( while (read_count < HDMI_PLL_POLL_MAX_READS) {
(io->pll_base + QSERDES_COM_C_READY_STATUS), status = MDSS_PLL_REG_R(io->pll_base,
status, ((status & BIT(0)) == 1), QSERDES_COM_C_READY_STATUS);
HDMI_PLL_POLL_MAX_READS, if ((status & BIT(0)) == 1) {
HDMI_PLL_POLL_TIMEOUT_US)) {
DEV_DBG("%s: C READY\n", __func__);
pll_locked = 1; pll_locked = 1;
} else { DEV_DBG("%s: C READY\n", __func__);
DEV_ERR("%s: C READY TIMEOUT\n", __func__); break;
}
udelay(HDMI_PLL_POLL_TIMEOUT_US);
read_count++;
}
if (read_count == HDMI_PLL_POLL_MAX_READS) {
pll_locked = 0; pll_locked = 0;
DEV_ERR("%s: C READY TIMEOUT\n", __func__);
} }
mdss_pll_resource_enable(io, false); mdss_pll_resource_enable(io, false);
@ -2062,20 +2073,25 @@ static int hdmi_8996_v2_perform_sw_calibration(struct clk *c)
struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);
struct mdss_pll_resources *io = vco->priv; struct mdss_pll_resources *io = vco->priv;
u32 vco_code1, vco_code2, integral_loop, ready_poll; u32 vco_code1, vco_code2, integral_loop, ready_poll;
u32 read_count = 0;
if (!readl_poll_timeout_atomic( while (read_count < (HDMI_PLL_POLL_MAX_READS << 1)) {
(io->pll_base + QSERDES_COM_C_READY_STATUS), ready_poll = MDSS_PLL_REG_R(io->pll_base,
ready_poll, ((ready_poll & BIT(0)) == 1), QSERDES_COM_C_READY_STATUS);
HDMI_PLL_POLL_MAX_READS, if ((ready_poll & BIT(0)) == 1) {
HDMI_PLL_POLL_TIMEOUT_US << 1)) {
DEV_DBG("%s: C READY\n", __func__);
ready_poll = 1; ready_poll = 1;
} else { DEV_DBG("%s: C READY\n", __func__);
DEV_DBG("%s: C READY TIMEOUT, TRYING SW CALIBRATION\n", break;
__func__); }
ready_poll = 0; udelay(HDMI_PLL_POLL_TIMEOUT_US);
read_count++;
} }
if (read_count == (HDMI_PLL_POLL_MAX_READS << 1)) {
ready_poll = 0;
DEV_DBG("%s: C READY TIMEOUT, TRYING SW CALIBRATION\n",
__func__);
}
vco_code1 = MDSS_PLL_REG_R(io->pll_base, vco_code1 = MDSS_PLL_REG_R(io->pll_base,
QSERDES_COM_PLLCAL_CODE1_STATUS); QSERDES_COM_PLLCAL_CODE1_STATUS);