evie/android_kernel_oneplus_msm8998
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Merge "msm: mdss: fix truncation of 64 bit for clk rate"

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Linux Build Service Account 2016-09-24 02:00:52 -07:00 • committed by Gerrit - the friendly Code Review server
commit 463b2ded6a
3 changed files with 14 additions and 12 deletions
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15
drivers/video/fbdev/msm/mdss_mdp_ctl.c
View file

@ -91,7 +91,7 @@ static inline u64 apply_inverse_fudge_factor(u64 val,
static DEFINE_MUTEX(mdss_mdp_ctl_lock);
static inline u32 mdss_mdp_get_pclk_rate(struct mdss_mdp_ctl *ctl)
static inline u64 mdss_mdp_get_pclk_rate(struct mdss_mdp_ctl *ctl)
{
struct mdss_panel_info *pinfo = &ctl->panel_data->panel_info;
@ -1564,9 +1564,9 @@ static void __mdss_mdp_perf_calc_ctl_helper(struct mdss_mdp_ctl *ctl,
perf->prefill_bytes += tmp.prefill_bytes;
if (ctl->intf_type) {
u32 clk_rate = mdss_mdp_get_pclk_rate(ctl);
u64 clk_rate = mdss_mdp_get_pclk_rate(ctl);
/* minimum clock rate due to inefficiency in 3dmux */
clk_rate = mult_frac(clk_rate >> 1, 9, 8);
clk_rate = DIV_ROUND_UP_ULL((clk_rate >> 1) * 9, 8);
if (clk_rate > perf->mdp_clk_rate)
perf->mdp_clk_rate = clk_rate;
}
@ -5358,7 +5358,8 @@ int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl,
ktime_t *wakeup_time)
{
struct mdss_panel_info *pinfo;
u32 clk_rate, clk_period;
u64 clk_rate;
u32 clk_period;
u32 current_line, total_line;
u32 time_of_line, time_to_vsync, adjust_line_ns;
@ -5373,7 +5374,7 @@ int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl,
clk_rate = mdss_mdp_get_pclk_rate(ctl);
clk_rate /= 1000; /* in kHz */
clk_rate = DIV_ROUND_UP_ULL(clk_rate, 1000); /* in kHz */
if (!clk_rate)
return -EINVAL;
@ -5382,7 +5383,7 @@ int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl,
* accuracy with high pclk rate and this number is in 17 bit
* range.
*/
clk_period = 1000000000 / clk_rate;
clk_period = DIV_ROUND_UP_ULL(1000000000, clk_rate);
if (!clk_period)
return -EINVAL;
@ -5421,7 +5422,7 @@ int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl,
*wakeup_time = ktime_add_ns(current_time, time_to_vsync);
pr_debug("clk_rate=%dkHz clk_period=%d cur_line=%d tot_line=%d\n",
pr_debug("clk_rate=%lldkHz clk_period=%d cur_line=%d tot_line=%d\n",
clk_rate, clk_period, current_line, total_line);
pr_debug("time_to_vsync=%d current_time=%d wakeup_time=%d\n",
time_to_vsync, (int)ktime_to_ms(current_time),

7
drivers/video/fbdev/msm/mdss_mdp_intf_video.c
View file

@ -316,7 +316,8 @@ static void mdss_mdp_video_intf_recovery(void *data, int event)
struct mdss_mdp_ctl *ctl = data;
struct mdss_panel_info *pinfo;
u32 line_cnt, min_ln_cnt, active_lns_cnt;
u32 clk_rate, clk_period, time_of_line;
u64 clk_rate;
u32 clk_period, time_of_line;
u32 delay;
if (!data) {
@ -344,7 +345,7 @@ static void mdss_mdp_video_intf_recovery(void *data, int event)
pinfo->mipi.dsi_pclk_rate :
pinfo->clk_rate);
clk_rate /= 1000; /* in kHz */
clk_rate = DIV_ROUND_UP_ULL(clk_rate, 1000); /* in kHz */
if (!clk_rate) {
pr_err("Unable to get proper clk_rate\n");
return;
@ -354,7 +355,7 @@ static void mdss_mdp_video_intf_recovery(void *data, int event)
* accuracy with high pclk rate and this number is in 17 bit
* range.
*/
clk_period = 1000000000 / clk_rate;
clk_period = DIV_ROUND_UP_ULL(1000000000, clk_rate);
if (!clk_period) {
pr_err("Unable to calculate clock period\n");
return;

4
drivers/video/fbdev/msm/mdss_panel.c
View file

@ -426,8 +426,8 @@ int mdss_panel_debugfs_panel_setup(struct mdss_panel_debugfs_info *debugfs_info,
(u32 *)&debugfs_info->panel_info.min_fps);
debugfs_create_u32("max_refresh_rate", 0644, debugfs_info->root,
(u32 *)&debugfs_info->panel_info.max_fps);
debugfs_create_u32("clk_rate", 0644, debugfs_info->root,
(u32 *)&debugfs_info->panel_info.clk_rate);
debugfs_create_u64("clk_rate", 0644, debugfs_info->root,
(u64 *)&debugfs_info->panel_info.clk_rate);
debugfs_create_u32("bl_min", 0644, debugfs_info->root,
(u32 *)&debugfs_info->panel_info.bl_min);
debugfs_create_u32("bl_max", 0644, debugfs_info->root,