Merge "spmi: pmic-arb: correct support for up to 512 APIDs"
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46f02a2de6
1 changed files with 47 additions and 40 deletions
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@ -97,6 +97,17 @@ enum pmic_arb_cmd_op_code {
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/* interrupt enable bit */
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#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
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#define HWIRQ(slave_id, periph_id, irq_id, apid) \
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((((slave_id) & 0xF) << 28) | \
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(((periph_id) & 0xFF) << 20) | \
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(((irq_id) & 0x7) << 16) | \
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(((apid) & 0x1FF) << 0))
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#define HWIRQ_SID(hwirq) (((hwirq) >> 28) & 0xF)
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#define HWIRQ_PER(hwirq) (((hwirq) >> 20) & 0xFF)
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#define HWIRQ_IRQ(hwirq) (((hwirq) >> 16) & 0x7)
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#define HWIRQ_APID(hwirq) (((hwirq) >> 0) & 0x1FF)
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struct pmic_arb_ver_ops;
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struct apid_data {
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@ -172,7 +183,7 @@ struct spmi_pmic_arb {
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struct pmic_arb_ver_ops {
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const char *ver_str;
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int (*ppid_to_apid)(struct spmi_pmic_arb *pa, u8 sid, u16 addr,
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u8 *apid);
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u16 *apid);
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int (*mode)(struct spmi_pmic_arb *dev, u8 sid, u16 addr,
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mode_t *mode);
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/* spmi commands (read_cmd, write_cmd, cmd) functionality */
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@ -181,10 +192,10 @@ struct pmic_arb_ver_ops {
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u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
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int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
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/* Interrupts controller functionality (offset of PIC registers) */
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u32 (*owner_acc_status)(u8 m, u8 n);
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u32 (*acc_enable)(u8 n);
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u32 (*irq_status)(u8 n);
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u32 (*irq_clear)(u8 n);
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u32 (*owner_acc_status)(u8 m, u16 n);
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u32 (*acc_enable)(u16 n);
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u32 (*irq_status)(u16 n);
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u32 (*irq_clear)(u16 n);
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};
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static inline void pmic_arb_base_write(struct spmi_pmic_arb *pa,
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@ -466,8 +477,8 @@ static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
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size_t len)
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{
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struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 sid = d->hwirq >> 24;
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u8 per = d->hwirq >> 16;
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u8 sid = HWIRQ_SID(d->hwirq);
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u8 per = HWIRQ_PER(d->hwirq);
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if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
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(per << 8) + reg, buf, len))
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@ -479,8 +490,8 @@ static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
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static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
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{
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struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 sid = d->hwirq >> 24;
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u8 per = d->hwirq >> 16;
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u8 sid = HWIRQ_SID(d->hwirq);
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u8 per = HWIRQ_PER(d->hwirq);
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if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
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(per << 8) + reg, buf, len))
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@ -489,7 +500,7 @@ static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
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d->irq);
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}
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static void cleanup_irq(struct spmi_pmic_arb *pa, u8 apid, int id)
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static void cleanup_irq(struct spmi_pmic_arb *pa, u16 apid, int id)
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{
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u16 ppid = pa->apid_data[apid].ppid;
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u8 sid = ppid >> 8;
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@ -514,20 +525,19 @@ static void cleanup_irq(struct spmi_pmic_arb *pa, u8 apid, int id)
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irq_mask, ppid);
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}
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static void periph_interrupt(struct spmi_pmic_arb *pa, u8 apid)
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static void periph_interrupt(struct spmi_pmic_arb *pa, u16 apid)
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{
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unsigned int irq;
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u32 status;
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int id;
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u8 sid = (pa->apid_data[apid].ppid >> 8) & 0xF;
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u8 per = pa->apid_data[apid].ppid & 0xFF;
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status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid));
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while (status) {
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id = ffs(status) - 1;
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status &= ~BIT(id);
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irq = irq_find_mapping(pa->domain,
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pa->apid_data[apid].ppid << 16
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| id << 8
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| apid);
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irq = irq_find_mapping(pa->domain, HWIRQ(sid, per, id, apid));
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if (irq == 0) {
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cleanup_irq(pa, apid, id);
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continue;
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@ -568,8 +578,8 @@ static void pmic_arb_chained_irq(struct irq_desc *desc)
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static void qpnpint_irq_ack(struct irq_data *d)
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{
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struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 irq = d->hwirq >> 8;
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u8 apid = d->hwirq;
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u16 apid = HWIRQ_APID(d->hwirq);
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u8 data;
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writel_relaxed(BIT(irq), pa->intr + pa->ver_ops->irq_clear(apid));
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@ -580,7 +590,7 @@ static void qpnpint_irq_ack(struct irq_data *d)
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static void qpnpint_irq_mask(struct irq_data *d)
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{
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u8 irq = d->hwirq >> 8;
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u8 data = BIT(irq);
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qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
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@ -589,8 +599,8 @@ static void qpnpint_irq_mask(struct irq_data *d)
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static void qpnpint_irq_unmask(struct irq_data *d)
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{
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struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d);
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u8 irq = d->hwirq >> 8;
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u8 apid = d->hwirq;
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u16 apid = HWIRQ_APID(d->hwirq);
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u8 buf[2];
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writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
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@ -612,7 +622,7 @@ static void qpnpint_irq_unmask(struct irq_data *d)
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static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct spmi_pmic_arb_qpnpint_type type;
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u8 irq = d->hwirq >> 8;
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u8 bit_mask_irq = BIT(irq);
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qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
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@ -649,7 +659,7 @@ static int qpnpint_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which,
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bool *state)
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{
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u8 irq = d->hwirq >> 8;
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u8 irq = HWIRQ_IRQ(d->hwirq);
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u8 status = 0;
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if (which != IRQCHIP_STATE_LINE_LEVEL)
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@ -681,7 +691,7 @@ static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
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{
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struct spmi_pmic_arb *pa = d->host_data;
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int rc;
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u8 apid;
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u16 apid;
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dev_dbg(&pa->spmic->dev,
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"intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
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@ -709,10 +719,7 @@ static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
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if (apid < pa->min_apid)
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pa->min_apid = apid;
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*out_hwirq = (intspec[0] & 0xF) << 24
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| (intspec[1] & 0xFF) << 16
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| (intspec[2] & 0x7) << 8
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| apid;
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*out_hwirq = HWIRQ(intspec[0], intspec[1], intspec[2], apid);
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*out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
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dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
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@ -735,7 +742,7 @@ static int qpnpint_irq_domain_map(struct irq_domain *d,
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}
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static int
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pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u8 *apid)
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pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid)
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{
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u16 ppid = sid << 8 | ((addr >> 8) & 0xFF);
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u32 *mapping_table = pa->mapping_table;
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@ -834,7 +841,7 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pa, u16 ppid)
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}
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static int
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pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u8 *apid)
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pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u16 *apid)
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{
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u16 ppid = (sid << 8) | (addr >> 8);
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u16 apid_valid;
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@ -852,7 +859,7 @@ pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u8 *apid)
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static int
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pmic_arb_mode_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode)
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{
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u8 apid;
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u16 apid;
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int rc;
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rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid);
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@ -871,7 +878,7 @@ pmic_arb_mode_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode)
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static int
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pmic_arb_offset_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u32 *offset)
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{
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u8 apid;
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u16 apid;
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int rc;
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rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid);
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@ -892,47 +899,47 @@ static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
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return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
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}
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static u32 pmic_arb_owner_acc_status_v1(u8 m, u8 n)
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static u32 pmic_arb_owner_acc_status_v1(u8 m, u16 n)
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{
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return 0x20 * m + 0x4 * n;
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}
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static u32 pmic_arb_owner_acc_status_v2(u8 m, u8 n)
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static u32 pmic_arb_owner_acc_status_v2(u8 m, u16 n)
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{
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return 0x100000 + 0x1000 * m + 0x4 * n;
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}
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static u32 pmic_arb_owner_acc_status_v3(u8 m, u8 n)
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static u32 pmic_arb_owner_acc_status_v3(u8 m, u16 n)
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{
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return 0x200000 + 0x1000 * m + 0x4 * n;
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}
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static u32 pmic_arb_acc_enable_v1(u8 n)
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static u32 pmic_arb_acc_enable_v1(u16 n)
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{
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return 0x200 + 0x4 * n;
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}
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static u32 pmic_arb_acc_enable_v2(u8 n)
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static u32 pmic_arb_acc_enable_v2(u16 n)
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{
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return 0x1000 * n;
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}
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static u32 pmic_arb_irq_status_v1(u8 n)
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static u32 pmic_arb_irq_status_v1(u16 n)
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{
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return 0x600 + 0x4 * n;
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}
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static u32 pmic_arb_irq_status_v2(u8 n)
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static u32 pmic_arb_irq_status_v2(u16 n)
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{
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return 0x4 + 0x1000 * n;
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}
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static u32 pmic_arb_irq_clear_v1(u8 n)
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static u32 pmic_arb_irq_clear_v1(u16 n)
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{
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return 0xA00 + 0x4 * n;
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}
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static u32 pmic_arb_irq_clear_v2(u8 n)
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static u32 pmic_arb_irq_clear_v2(u16 n)
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{
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return 0x8 + 0x1000 * n;
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}
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