Merge "spi: spi_qsd: Improve latencies for small transfers"
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4802720f7b
2 changed files with 133 additions and 76 deletions
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@ -1,4 +1,4 @@
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/* Copyright (c) 2008-2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2008-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -45,6 +45,8 @@
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#include <linux/msm-bus-board.h>
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#include "spi_qsd.h"
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#define SPI_MAX_BYTES_PER_WORD (4)
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static int msm_spi_pm_resume_runtime(struct device *device);
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static int msm_spi_pm_suspend_runtime(struct device *device);
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static inline void msm_spi_dma_unmap_buffers(struct msm_spi *dd);
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@ -438,10 +440,12 @@ static void msm_spi_read_word_from_fifo(struct msm_spi *dd)
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u32 data_in;
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int i;
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int shift;
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int read_bytes = (dd->pack_words ?
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SPI_MAX_BYTES_PER_WORD : dd->bytes_per_word);
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data_in = readl_relaxed(dd->base + SPI_INPUT_FIFO);
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if (dd->read_buf) {
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for (i = 0; (i < dd->bytes_per_word) &&
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for (i = 0; (i < read_bytes) &&
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dd->rx_bytes_remaining; i++) {
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/* The data format depends on bytes_per_word:
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4 bytes: 0x12345678
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@ -454,8 +458,8 @@ static void msm_spi_read_word_from_fifo(struct msm_spi *dd)
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dd->rx_bytes_remaining--;
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}
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} else {
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if (dd->rx_bytes_remaining >= dd->bytes_per_word)
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dd->rx_bytes_remaining -= dd->bytes_per_word;
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if (dd->rx_bytes_remaining >= read_bytes)
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dd->rx_bytes_remaining -= read_bytes;
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else
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dd->rx_bytes_remaining = 0;
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}
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@ -552,7 +556,7 @@ msm_spi_set_bpw_and_no_io_flags(struct msm_spi *dd, u32 *config, int n)
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if (n != (*config & SPI_CFG_N))
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*config = (*config & ~SPI_CFG_N) | n;
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if (dd->mode == SPI_BAM_MODE) {
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if (dd->tx_mode == SPI_BAM_MODE) {
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if (dd->read_buf == NULL)
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*config |= SPI_NO_INPUT;
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if (dd->write_buf == NULL)
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@ -617,25 +621,34 @@ static void msm_spi_set_spi_config(struct msm_spi *dd, int bpw)
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static void msm_spi_set_mx_counts(struct msm_spi *dd, u32 n_words)
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{
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/*
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* n_words cannot exceed fifo_size, and only one READ COUNT
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* interrupt is generated per transaction, so for transactions
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* larger than fifo size READ COUNT must be disabled.
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* For those transactions we usually move to Data Mover mode.
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* For FIFO mode:
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* - Set the MX_OUTPUT_COUNT/MX_INPUT_COUNT registers to 0
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* - Set the READ/WRITE_COUNT registers to 0 (infinite mode)
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* or num bytes (finite mode) if less than fifo worth of data.
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* For Block mode:
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* - Set the MX_OUTPUT/MX_INPUT_COUNT registers to num xfer bytes.
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* - Set the READ/WRITE_COUNT registers to 0.
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*/
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if (dd->mode == SPI_FIFO_MODE) {
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if (n_words <= dd->input_fifo_size) {
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writel_relaxed(n_words,
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dd->base + SPI_MX_READ_COUNT);
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msm_spi_set_write_count(dd, n_words);
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} else {
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writel_relaxed(0, dd->base + SPI_MX_READ_COUNT);
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msm_spi_set_write_count(dd, 0);
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}
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if (dd->qup_ver == SPI_QUP_VERSION_BFAM) {
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/* must be zero for FIFO */
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writel_relaxed(0, dd->base + SPI_MX_INPUT_COUNT);
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if (dd->tx_mode != SPI_BAM_MODE) {
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if (dd->tx_mode == SPI_FIFO_MODE) {
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if (n_words <= dd->input_fifo_size)
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msm_spi_set_write_count(dd, n_words);
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else
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msm_spi_set_write_count(dd, 0);
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writel_relaxed(0, dd->base + SPI_MX_OUTPUT_COUNT);
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}
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} else
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writel_relaxed(n_words, dd->base + SPI_MX_OUTPUT_COUNT);
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if (dd->rx_mode == SPI_FIFO_MODE) {
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if (n_words <= dd->input_fifo_size)
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writel_relaxed(n_words,
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dd->base + SPI_MX_READ_COUNT);
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else
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writel_relaxed(0,
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dd->base + SPI_MX_READ_COUNT);
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writel_relaxed(0, dd->base + SPI_MX_INPUT_COUNT);
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} else
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writel_relaxed(n_words, dd->base + SPI_MX_INPUT_COUNT);
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} else {
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/* must be zero for BAM and DMOV */
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writel_relaxed(0, dd->base + SPI_MX_READ_COUNT);
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@ -882,7 +895,7 @@ xfr_err:
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static int
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msm_spi_bam_next_transfer(struct msm_spi *dd)
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{
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if (dd->mode != SPI_BAM_MODE)
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if (dd->tx_mode != SPI_BAM_MODE)
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return 0;
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if (dd->tx_bytes_remaining > 0) {
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@ -901,7 +914,7 @@ msm_spi_bam_next_transfer(struct msm_spi *dd)
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static int msm_spi_dma_send_next(struct msm_spi *dd)
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{
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int ret = 0;
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if (dd->mode == SPI_BAM_MODE)
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if (dd->tx_mode == SPI_BAM_MODE)
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ret = msm_spi_bam_next_transfer(dd);
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return ret;
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}
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@ -932,32 +945,38 @@ static inline irqreturn_t msm_spi_qup_irq(int irq, void *dev_id)
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}
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op = readl_relaxed(dd->base + SPI_OPERATIONAL);
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writel_relaxed(op, dd->base + SPI_OPERATIONAL);
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/*
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* Ensure service flag was cleared before further
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* processing of interrupt.
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*/
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mb();
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if (op & SPI_OP_INPUT_SERVICE_FLAG) {
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writel_relaxed(SPI_OP_INPUT_SERVICE_FLAG,
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dd->base + SPI_OPERATIONAL);
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/*
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* Ensure service flag was cleared before further
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* processing of interrupt.
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*/
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mb();
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ret |= msm_spi_input_irq(irq, dev_id);
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}
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if (op & SPI_OP_OUTPUT_SERVICE_FLAG) {
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writel_relaxed(SPI_OP_OUTPUT_SERVICE_FLAG,
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dd->base + SPI_OPERATIONAL);
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/*
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* Ensure service flag was cleared before further
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* processing of interrupt.
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*/
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mb();
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ret |= msm_spi_output_irq(irq, dev_id);
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}
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if (dd->done) {
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if (dd->tx_mode != SPI_BAM_MODE) {
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if (!dd->rx_done) {
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if (dd->rx_bytes_remaining == 0)
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dd->rx_done = true;
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}
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if (!dd->tx_done) {
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if (!dd->tx_bytes_remaining &&
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(op & SPI_OP_IP_FIFO_NOT_EMPTY)) {
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dd->tx_done = true;
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}
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}
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}
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if (dd->tx_done && dd->rx_done) {
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msm_spi_set_state(dd, SPI_OP_STATE_RESET);
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dd->tx_done = false;
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dd->rx_done = false;
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complete(&dd->rx_transfer_complete);
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complete(&dd->tx_transfer_complete);
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dd->done = 0;
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}
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return ret;
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}
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@ -968,17 +987,23 @@ static irqreturn_t msm_spi_input_irq(int irq, void *dev_id)
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dd->stat_rx++;
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if (dd->mode == SPI_MODE_NONE)
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if (dd->rx_mode == SPI_MODE_NONE)
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return IRQ_HANDLED;
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if (dd->mode == SPI_FIFO_MODE) {
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if (dd->rx_mode == SPI_FIFO_MODE) {
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while ((readl_relaxed(dd->base + SPI_OPERATIONAL) &
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SPI_OP_IP_FIFO_NOT_EMPTY) &&
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(dd->rx_bytes_remaining > 0)) {
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msm_spi_read_word_from_fifo(dd);
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}
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if (dd->rx_bytes_remaining == 0)
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msm_spi_complete(dd);
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} else if (dd->rx_mode == SPI_BLOCK_MODE) {
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int count = 0;
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while (dd->rx_bytes_remaining &&
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(count < dd->input_block_size)) {
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msm_spi_read_word_from_fifo(dd);
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count += SPI_MAX_BYTES_PER_WORD;
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}
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}
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return IRQ_HANDLED;
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@ -989,18 +1014,20 @@ static void msm_spi_write_word_to_fifo(struct msm_spi *dd)
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u32 word;
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u8 byte;
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int i;
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int write_bytes =
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(dd->pack_words ? SPI_MAX_BYTES_PER_WORD : dd->bytes_per_word);
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word = 0;
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if (dd->write_buf) {
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for (i = 0; (i < dd->bytes_per_word) &&
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for (i = 0; (i < write_bytes) &&
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dd->tx_bytes_remaining; i++) {
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dd->tx_bytes_remaining--;
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byte = *dd->write_buf++;
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word |= (byte << (BITS_PER_BYTE * i));
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}
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} else
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if (dd->tx_bytes_remaining > dd->bytes_per_word)
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dd->tx_bytes_remaining -= dd->bytes_per_word;
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if (dd->tx_bytes_remaining > write_bytes)
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dd->tx_bytes_remaining -= write_bytes;
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else
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dd->tx_bytes_remaining = 0;
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dd->write_xfr_cnt++;
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@ -1012,11 +1039,22 @@ static inline void msm_spi_write_rmn_to_fifo(struct msm_spi *dd)
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{
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int count = 0;
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while ((dd->tx_bytes_remaining > 0) && (count < dd->input_fifo_size) &&
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!(readl_relaxed(dd->base + SPI_OPERATIONAL) &
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SPI_OP_OUTPUT_FIFO_FULL)) {
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msm_spi_write_word_to_fifo(dd);
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count++;
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if (dd->tx_mode == SPI_FIFO_MODE) {
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while ((dd->tx_bytes_remaining > 0) &&
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(count < dd->input_fifo_size) &&
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!(readl_relaxed(dd->base + SPI_OPERATIONAL)
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& SPI_OP_OUTPUT_FIFO_FULL)) {
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msm_spi_write_word_to_fifo(dd);
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count++;
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}
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}
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if (dd->tx_mode == SPI_BLOCK_MODE) {
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while (dd->tx_bytes_remaining &&
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(count < dd->output_block_size)) {
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msm_spi_write_word_to_fifo(dd);
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count += SPI_MAX_BYTES_PER_WORD;
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}
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}
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}
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@ -1026,11 +1064,11 @@ static irqreturn_t msm_spi_output_irq(int irq, void *dev_id)
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dd->stat_tx++;
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if (dd->mode == SPI_MODE_NONE)
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if (dd->tx_mode == SPI_MODE_NONE)
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return IRQ_HANDLED;
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/* Output FIFO is empty. Transmit any outstanding write data. */
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if (dd->mode == SPI_FIFO_MODE)
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if ((dd->tx_mode == SPI_FIFO_MODE) || (dd->tx_mode == SPI_BLOCK_MODE))
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msm_spi_write_rmn_to_fifo(dd);
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return IRQ_HANDLED;
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@ -1106,7 +1144,7 @@ error:
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static int msm_spi_dma_map_buffers(struct msm_spi *dd)
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{
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int ret = 0;
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if (dd->mode == SPI_BAM_MODE)
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if (dd->tx_mode == SPI_BAM_MODE)
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ret = msm_spi_bam_map_buffers(dd);
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return ret;
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}
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@ -1135,7 +1173,7 @@ static void msm_spi_bam_unmap_buffers(struct msm_spi *dd)
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static inline void msm_spi_dma_unmap_buffers(struct msm_spi *dd)
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{
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if (dd->mode == SPI_BAM_MODE)
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if (dd->tx_mode == SPI_BAM_MODE)
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msm_spi_bam_unmap_buffers(dd);
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}
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@ -1197,9 +1235,11 @@ static void
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msm_spi_set_transfer_mode(struct msm_spi *dd, u8 bpw, u32 read_count)
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{
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if (msm_spi_use_dma(dd, dd->cur_transfer, bpw)) {
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dd->mode = SPI_BAM_MODE;
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dd->tx_mode = SPI_BAM_MODE;
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dd->rx_mode = SPI_BAM_MODE;
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} else {
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dd->mode = SPI_FIFO_MODE;
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dd->rx_mode = SPI_FIFO_MODE;
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dd->tx_mode = SPI_FIFO_MODE;
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dd->read_len = dd->cur_transfer->len;
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dd->write_len = dd->cur_transfer->len;
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}
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@ -1215,14 +1255,19 @@ static void msm_spi_set_qup_io_modes(struct msm_spi *dd)
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spi_iom = readl_relaxed(dd->base + SPI_IO_MODES);
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/* Set input and output transfer mode: FIFO, DMOV, or BAM */
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spi_iom &= ~(SPI_IO_M_INPUT_MODE | SPI_IO_M_OUTPUT_MODE);
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spi_iom = (spi_iom | (dd->mode << OUTPUT_MODE_SHIFT));
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spi_iom = (spi_iom | (dd->mode << INPUT_MODE_SHIFT));
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/* Turn on packing for data mover */
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if (dd->mode == SPI_BAM_MODE)
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spi_iom = (spi_iom | (dd->tx_mode << OUTPUT_MODE_SHIFT));
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spi_iom = (spi_iom | (dd->rx_mode << INPUT_MODE_SHIFT));
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/* Always enable packing for all % 8 bits_per_word */
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if (dd->cur_transfer->bits_per_word &&
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((dd->cur_transfer->bits_per_word == 8) ||
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(dd->cur_transfer->bits_per_word == 16) ||
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(dd->cur_transfer->bits_per_word == 32))) {
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spi_iom |= SPI_IO_M_PACK_EN | SPI_IO_M_UNPACK_EN;
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else {
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dd->pack_words = true;
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} else {
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spi_iom &= ~(SPI_IO_M_PACK_EN | SPI_IO_M_UNPACK_EN);
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spi_iom |= SPI_IO_M_OUTPUT_BIT_SHIFT_EN;
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dd->pack_words = false;
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}
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/*if (dd->mode == SPI_BAM_MODE) {
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@ -1280,7 +1325,7 @@ static void msm_spi_set_qup_op_mask(struct msm_spi *dd)
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{
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/* mask INPUT and OUTPUT service flags in to prevent IRQs on FIFO status
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* change in BAM mode */
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u32 mask = (dd->mode == SPI_BAM_MODE) ?
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u32 mask = (dd->tx_mode == SPI_BAM_MODE) ?
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QUP_OP_MASK_OUTPUT_SERVICE_FLAG | QUP_OP_MASK_INPUT_SERVICE_FLAG
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: 0;
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writel_relaxed(mask, dd->base + QUP_OPERATIONAL_MASK);
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@ -1321,6 +1366,8 @@ static int msm_spi_process_transfer(struct msm_spi *dd)
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dd->rx_bytes_remaining = dd->cur_msg_len;
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dd->read_buf = dd->cur_transfer->rx_buf;
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dd->write_buf = dd->cur_transfer->tx_buf;
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dd->tx_done = false;
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dd->rx_done = false;
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init_completion(&dd->tx_transfer_complete);
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init_completion(&dd->rx_transfer_complete);
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if (dd->cur_transfer->bits_per_word)
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@ -1351,10 +1398,12 @@ static int msm_spi_process_transfer(struct msm_spi *dd)
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msm_spi_set_transfer_mode(dd, bpw, read_count);
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msm_spi_set_mx_counts(dd, read_count);
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if (dd->mode == SPI_BAM_MODE) {
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if (dd->tx_mode == SPI_BAM_MODE) {
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ret = msm_spi_dma_map_buffers(dd);
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if (ret < 0) {
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pr_err("Mapping DMA buffers\n");
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dd->tx_mode = SPI_MODE_NONE;
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dd->rx_mode = SPI_MODE_NONE;
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return ret;
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}
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}
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|
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@ -1368,11 +1417,11 @@ static int msm_spi_process_transfer(struct msm_spi *dd)
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the first. Restricting this to one write avoids contention
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issues and race conditions between this thread and the int handler
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*/
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if (dd->mode == SPI_FIFO_MODE) {
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if (dd->tx_mode != SPI_BAM_MODE) {
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if (msm_spi_prepare_for_write(dd))
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goto transfer_end;
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msm_spi_start_write(dd, read_count);
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} else if (dd->mode == SPI_BAM_MODE) {
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} else {
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if ((msm_spi_bam_begin_transfer(dd)) < 0) {
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dev_err(dd->dev, "%s: BAM transfer setup failed\n",
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__func__);
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@ -1388,11 +1437,11 @@ static int msm_spi_process_transfer(struct msm_spi *dd)
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* might fire before the first word is written resulting in a
|
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* possible race condition.
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*/
|
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if (dd->mode != SPI_BAM_MODE)
|
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if (dd->tx_mode != SPI_BAM_MODE)
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if (msm_spi_set_state(dd, SPI_OP_STATE_RUN)) {
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dev_warn(dd->dev,
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"%s: Failed to set QUP to run-state. Mode:%d",
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__func__, dd->mode);
|
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__func__, dd->tx_mode);
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goto transfer_end;
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}
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|
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@ -1422,10 +1471,11 @@ static int msm_spi_process_transfer(struct msm_spi *dd)
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msm_spi_udelay(dd->xfrs_delay_usec);
|
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transfer_end:
|
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if ((dd->mode == SPI_BAM_MODE) && status)
|
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if ((dd->tx_mode == SPI_BAM_MODE) && status)
|
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msm_spi_bam_flush(dd);
|
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msm_spi_dma_unmap_buffers(dd);
|
||||
dd->mode = SPI_MODE_NONE;
|
||||
dd->tx_mode = SPI_MODE_NONE;
|
||||
dd->rx_mode = SPI_MODE_NONE;
|
||||
|
||||
msm_spi_set_state(dd, SPI_OP_STATE_RESET);
|
||||
if (!dd->cur_transfer->cs_change)
|
||||
|
|
@ -2350,7 +2400,8 @@ static int init_resources(struct platform_device *pdev)
|
|||
pclk_enabled = 0;
|
||||
|
||||
dd->transfer_pending = 0;
|
||||
dd->mode = SPI_MODE_NONE;
|
||||
dd->tx_mode = SPI_MODE_NONE;
|
||||
dd->rx_mode = SPI_MODE_NONE;
|
||||
|
||||
rc = msm_spi_request_irq(dd, pdev, master);
|
||||
if (rc)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
|
@ -113,6 +113,8 @@
|
|||
#define INPUT_MODE_SHIFT QSD_REG(10) QUP_REG(12)
|
||||
|
||||
/* SPI_OPERATIONAL fields */
|
||||
#define SPI_OP_IN_BLK_RD_REQ_FLAG 0x00002000
|
||||
#define SPI_OP_OUT_BLK_WR_REQ_FLAG 0x00001000
|
||||
#define SPI_OP_MAX_INPUT_DONE_FLAG 0x00000800
|
||||
#define SPI_OP_MAX_OUTPUT_DONE_FLAG 0x00000400
|
||||
#define SPI_OP_INPUT_SERVICE_FLAG 0x00000200
|
||||
|
|
@ -318,7 +320,8 @@ struct msm_spi {
|
|||
bool transfer_pending;
|
||||
wait_queue_head_t continue_suspend;
|
||||
/* DMA data */
|
||||
enum msm_spi_mode mode;
|
||||
enum msm_spi_mode tx_mode;
|
||||
enum msm_spi_mode rx_mode;
|
||||
bool use_dma;
|
||||
int tx_dma_chan;
|
||||
int tx_dma_crci;
|
||||
|
|
@ -349,7 +352,8 @@ struct msm_spi {
|
|||
#endif
|
||||
struct msm_spi_platform_data *pdata; /* Platform data */
|
||||
/* When set indicates multiple transfers in a single message */
|
||||
bool done;
|
||||
bool rx_done;
|
||||
bool tx_done;
|
||||
u32 cur_msg_len;
|
||||
/* Used in FIFO mode to keep track of the transfer being processed */
|
||||
struct spi_transfer *cur_tx_transfer;
|
||||
|
|
@ -367,6 +371,7 @@ struct msm_spi {
|
|||
struct pinctrl_state *pins_active;
|
||||
struct pinctrl_state *pins_sleep;
|
||||
bool is_init_complete;
|
||||
bool pack_words;
|
||||
};
|
||||
|
||||
/* Forward declaration */
|
||||
|
|
@ -523,7 +528,8 @@ static inline void msm_spi_set_write_count(struct msm_spi *dd, int val)
|
|||
|
||||
static inline void msm_spi_complete(struct msm_spi *dd)
|
||||
{
|
||||
dd->done = 1;
|
||||
dd->tx_done = true;
|
||||
dd->rx_done = true;
|
||||
}
|
||||
|
||||
static inline void msm_spi_enable_error_flags(struct msm_spi *dd)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue