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clk: qcom: Add support for MMCC clock for MSMFalcon

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Add support for the multimedia clock controller found on MSMFalcon
based devices. This should allow most clocks for multimedia peripherals
which includes display, video, camera etc.

Change-Id: If8aa0b094af5ff82fe66c95e3ef2f13632950d2e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2016-09-24 16:32:36 +05:30
parent a0b8ac8a28
commit 48638ac98d
6 changed files with 3105 additions and 40 deletions
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1
Documentation/devicetree/bindings/clock/qcom,mmcc.txt
View file

@ -10,6 +10,7 @@ Required properties :
"qcom,mmcc-msm8960"
"qcom,mmcc-msm8974"
"qcom,mmcc-msm8996"
"qcom,mmcc-msmfalcon"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1

10
drivers/clk/qcom/Kconfig
View file

@ -173,6 +173,16 @@ config MSM_GPUCC_FALCON
Say Y if you want to support graphics controller devices which will
be required to enable those device.
config MSM_MMCC_FALCON
tristate "MSMFALCON Multimedia Clock Controller"
select MSM_GCC_FALCON
depends on COMMON_CLK_QCOM
help
Support for the multimedia clock controller on Qualcomm Technologies, Inc
MSMfalcon devices.
Say Y if you want to support multimedia devices such as display,
video encode/decode, camera, etc.
config QCOM_HFPLL
tristate "High-Frequency PLL (HFPLL) Clock Controller"
depends on COMMON_CLK_QCOM

1
drivers/clk/qcom/Makefile
View file

@ -30,6 +30,7 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o
obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
obj-$(CONFIG_KRAITCC) += krait-cc.o

3036
drivers/clk/qcom/mmcc-msmfalcon.c Normal file
View file

File diff suppressed because it is too large Load diff

15
drivers/clk/qcom/vdd-level-falcon.h
View file

@ -116,6 +116,21 @@
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_MMSS_PLL_DIG_FMAX_MAP1(l1, f1) \
.vdd_class = &vdd_mx, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
}, \
.num_rate_max = VDD_DIG_NUM
#define VDD_MMSS_PLL_DIG_FMAX_MAP2(l1, f1, l2, f2) \
.vdd_class = &vdd_mx, \
.rate_max = (unsigned long[VDD_DIG_NUM]) { \
[VDD_DIG_##l1] = (f1), \
[VDD_DIG_##l2] = (f2), \
}, \
.num_rate_max = VDD_DIG_NUM
enum vdd_dig_levels {
VDD_DIG_NONE,
VDD_DIG_MIN, /* MIN SVS */

82
include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
View file

@ -159,46 +159,47 @@
#define MMSS_MDSS_AXI_CLK 142
#define MMSS_MDSS_BYTE0_CLK 143
#define MMSS_MDSS_BYTE0_INTF_CLK 144
#define MMSS_MDSS_BYTE1_CLK 145
#define MMSS_MDSS_BYTE1_INTF_CLK 146
#define MMSS_MDSS_DP_AUX_CLK 147
#define MMSS_MDSS_DP_CRYPTO_CLK 148
#define MMSS_MDSS_DP_GTC_CLK 149
#define MMSS_MDSS_DP_LINK_CLK 150
#define MMSS_MDSS_DP_LINK_INTF_CLK 151
#define MMSS_MDSS_DP_PIXEL_CLK 152
#define MMSS_MDSS_ESC0_CLK 153
#define MMSS_MDSS_ESC1_CLK 154
#define MMSS_MDSS_HDMI_DP_AHB_CLK 155
#define MMSS_MDSS_MDP_CLK 156
#define MMSS_MDSS_PCLK0_CLK 157
#define MMSS_MDSS_PCLK1_CLK 158
#define MMSS_MDSS_ROT_CLK 159
#define MMSS_MDSS_VSYNC_CLK 160
#define MMSS_MISC_AHB_CLK 161
#define MMSS_MISC_CXO_CLK 162
#define MMSS_MNOC_AHB_CLK 163
#define MMSS_SNOC_DVM_AXI_CLK 164
#define MMSS_THROTTLE_CAMSS_AHB_CLK 165
#define MMSS_THROTTLE_CAMSS_AXI_CLK 166
#define MMSS_THROTTLE_CAMSS_CXO_CLK 167
#define MMSS_THROTTLE_MDSS_AHB_CLK 168
#define MMSS_THROTTLE_MDSS_AXI_CLK 169
#define MMSS_THROTTLE_MDSS_CXO_CLK 170
#define MMSS_THROTTLE_VIDEO_AHB_CLK 171
#define MMSS_THROTTLE_VIDEO_AXI_CLK 172
#define MMSS_THROTTLE_VIDEO_CXO_CLK 173
#define MMSS_VIDEO_AHB_CLK 174
#define MMSS_VIDEO_AXI_CLK 175
#define MMSS_VIDEO_CORE_CLK 176
#define MMSS_VIDEO_SUBCORE0_CLK 177
#define PCLK0_CLK_SRC 178
#define PCLK1_CLK_SRC 179
#define ROT_CLK_SRC 180
#define VFE0_CLK_SRC 181
#define VFE1_CLK_SRC 182
#define VIDEO_CORE_CLK_SRC 183
#define VSYNC_CLK_SRC 184
#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 145
#define MMSS_MDSS_BYTE1_CLK 146
#define MMSS_MDSS_BYTE1_INTF_CLK 147
#define MMSS_MDSS_DP_AUX_CLK 148
#define MMSS_MDSS_DP_CRYPTO_CLK 149
#define MMSS_MDSS_DP_GTC_CLK 150
#define MMSS_MDSS_DP_LINK_CLK 151
#define MMSS_MDSS_DP_LINK_INTF_CLK 152
#define MMSS_MDSS_DP_PIXEL_CLK 153
#define MMSS_MDSS_ESC0_CLK 154
#define MMSS_MDSS_ESC1_CLK 155
#define MMSS_MDSS_HDMI_DP_AHB_CLK 156
#define MMSS_MDSS_MDP_CLK 157
#define MMSS_MDSS_PCLK0_CLK 158
#define MMSS_MDSS_PCLK1_CLK 159
#define MMSS_MDSS_ROT_CLK 160
#define MMSS_MDSS_VSYNC_CLK 161
#define MMSS_MISC_AHB_CLK 162
#define MMSS_MISC_CXO_CLK 163
#define MMSS_MNOC_AHB_CLK 164
#define MMSS_SNOC_DVM_AXI_CLK 165
#define MMSS_THROTTLE_CAMSS_AHB_CLK 166
#define MMSS_THROTTLE_CAMSS_AXI_CLK 167
#define MMSS_THROTTLE_CAMSS_CXO_CLK 168
#define MMSS_THROTTLE_MDSS_AHB_CLK 169
#define MMSS_THROTTLE_MDSS_AXI_CLK 170
#define MMSS_THROTTLE_MDSS_CXO_CLK 171
#define MMSS_THROTTLE_VIDEO_AHB_CLK 172
#define MMSS_THROTTLE_VIDEO_AXI_CLK 173
#define MMSS_THROTTLE_VIDEO_CXO_CLK 174
#define MMSS_VIDEO_AHB_CLK 175
#define MMSS_VIDEO_AXI_CLK 176
#define MMSS_VIDEO_CORE_CLK 177
#define MMSS_VIDEO_SUBCORE0_CLK 178
#define PCLK0_CLK_SRC 179
#define PCLK1_CLK_SRC 180
#define ROT_CLK_SRC 181
#define VFE0_CLK_SRC 182
#define VFE1_CLK_SRC 183
#define VIDEO_CORE_CLK_SRC 184
#define VSYNC_CLK_SRC 185
#define BIMC_SMMU_GDSC 0
#define CAMSS_CPP_GDSC 1
@ -209,5 +210,6 @@
#define VIDEO_SUBCORE0_GDSC 6
#define VIDEO_TOP_GDSC 7
#define CAMSS_MICRO_BCR 0
#endif