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dmaengine: at_xdmac: fix spurious flag status for mem2mem transfers

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commit 95da0c19d164f6df0b71a5187950f47d4b746e91 upstream.

When setting the channel configuration register, the perid field is not
set to 0 since it is useless for mem2mem transfers. Unfortunately, a
device has 0 as perid. It could cause spurious flags status because
the controller could mix some events from the two channels.
For that reason, use the highest perid value for mem2mem transfers since it
doesn't match the perid of other devices.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ludovic Desroches 2015-11-23 14:09:39 +01:00 • committed by Greg Kroah-Hartman
parent fff40ee4d2
commit 4916339188
1 changed files with 15 additions and 3 deletions
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18
drivers/dma/at_xdmac.c
View file

@ -864,8 +864,12 @@ at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
* access. Hopefully we can access DDR through both ports (at least on * access. Hopefully we can access DDR through both ports (at least on
* SAMA5D4x), so we can use the same interface for source and dest, * SAMA5D4x), so we can use the same interface for source and dest,
* that solves the fact we don't know the direction. * that solves the fact we don't know the direction.
* ERRATA: Even if useless for memory transfers, the PERID has to not
* match the one of another channel. If not, it could lead to spurious
* flag status.
*/ */
u32 chan_cc = AT_XDMAC_CC_DIF(0) u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
| AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0) | AT_XDMAC_CC_SIF(0)
| AT_XDMAC_CC_MBSIZE_SIXTEEN | AT_XDMAC_CC_MBSIZE_SIXTEEN
| AT_XDMAC_CC_TYPE_MEM_TRAN; | AT_XDMAC_CC_TYPE_MEM_TRAN;
@ -1042,8 +1046,12 @@ at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
* access DDR through both ports (at least on SAMA5D4x), so we can use * access DDR through both ports (at least on SAMA5D4x), so we can use
* the same interface for source and dest, that solves the fact we * the same interface for source and dest, that solves the fact we
* don't know the direction. * don't know the direction.
* ERRATA: Even if useless for memory transfers, the PERID has to not
* match the one of another channel. If not, it could lead to spurious
* flag status.
*/ */
u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
| AT_XDMAC_CC_DAM_INCREMENTED_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM | AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0) | AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0) | AT_XDMAC_CC_SIF(0)
@ -1144,8 +1152,12 @@ static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
* access. Hopefully we can access DDR through both ports (at least on * access. Hopefully we can access DDR through both ports (at least on
* SAMA5D4x), so we can use the same interface for source and dest, * SAMA5D4x), so we can use the same interface for source and dest,
* that solves the fact we don't know the direction. * that solves the fact we don't know the direction.
* ERRATA: Even if useless for memory transfers, the PERID has to not
* match the one of another channel. If not, it could lead to spurious
* flag status.
*/ */
u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM u32 chan_cc = AT_XDMAC_CC_PERID(0x3f)
| AT_XDMAC_CC_DAM_UBS_AM
| AT_XDMAC_CC_SAM_INCREMENTED_AM | AT_XDMAC_CC_SAM_INCREMENTED_AM
| AT_XDMAC_CC_DIF(0) | AT_XDMAC_CC_DIF(0)
| AT_XDMAC_CC_SIF(0) | AT_XDMAC_CC_SIF(0)