From 49f4491edc0fcca082f4ca2c8f4068dda738e06d Mon Sep 17 00:00:00 2001 From: Zhen Kong Date: Fri, 4 Mar 2016 17:45:31 -0800 Subject: [PATCH] ARM: dts: msm: correct CE clock setting for crypto driver on msm8996 Correct CE clock setting for crypto drivers, core_clk_src should link to voting clock; otherwise, ce1 clock is set to be only half of 171M HZ during crypto operations. Change-Id: I0d9e048381a83d4788bf4f700d788137b59bd368 Signed-off-by: Zhen Kong --- arch/arm/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi index 2b46c4041438..d62862ebb96a 100644 --- a/arch/arm/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -2506,7 +2506,7 @@ <55 512 3936000 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; - clocks = <&clock_gcc clk_ce1_clk>, + clocks = <&clock_gcc clk_qcrypto_ce1_clk>, <&clock_gcc clk_qcrypto_ce1_clk>, <&clock_gcc clk_gcc_ce1_ahb_m_clk>, <&clock_gcc clk_gcc_ce1_axi_m_clk>; @@ -2536,7 +2536,7 @@ <55 512 3936000 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; - clocks = <&clock_gcc clk_ce1_clk>, + clocks = <&clock_gcc clk_qcedev_ce1_clk>, <&clock_gcc clk_qcedev_ce1_clk>, <&clock_gcc clk_gcc_ce1_ahb_m_clk>, <&clock_gcc clk_gcc_ce1_axi_m_clk>;