evie/android_kernel_oneplus_msm8998
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r8169: use correct barrier between cacheable and non-cacheable memory

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r8169 needs certain writes to be visible to other CPUs or the NIC before
touching the hardware, but was using smp_wmb() which is only required to
order cacheable memory access. Switch to wmb() which is required to
order both cacheable and non-cacheable memory.

Noticed by Catalin Marinas and Paul Mackerras.

Signed-off-by: David Dillow <dave@thedillows.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David Dillow 2010-03-03 16:33:10 +00:00 • committed by David S. Miller
parent d0021b252e
commit 4c020a961a
1 changed files with 2 additions and 2 deletions
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4
drivers/net/r8169.c
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@ -4270,7 +4270,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
tp->cur_tx += frags + 1; tp->cur_tx += frags + 1;
smp_wmb(); wmb();
RTL_W8(TxPoll, NPQ); /* set polling bit */ RTL_W8(TxPoll, NPQ); /* set polling bit */
@ -4621,7 +4621,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)
* until it does. * until it does.
*/ */
tp->intr_mask = 0xffff; tp->intr_mask = 0xffff;
smp_wmb(); wmb();
RTL_W16(IntrMask, tp->intr_event); RTL_W16(IntrMask, tp->intr_event);
} }