msm: mdss: add support for multiple DSI host escape clk frequencies
Some panels have low escape clock requirements based on which the host escape clock should be configured. Add support to configure host escape clock based on the panel escape clock. By default, the host would be configured for an escape clock of 19.2MHz. Change-Id: If791ffb4d49dd97424366042ee35bd4ecda5c185 Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
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Ashish Garg
parent
6f55033ecf
commit
4cd60f6e04
5 changed files with 28 additions and 7 deletions
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@ -271,6 +271,8 @@ Optional properties:
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"trigger_sw_te" = Software trigger and TE
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- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel.
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60 = 60 frames per second (default)
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- qcom,mdss-dsi-host-esc-clk-freq-hz: Specifies the escape clock needed for the host.
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19200000 = 19.2 MHz (default)
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- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz.
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0 = default value.
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- qcom,mdss-mdp-kickoff-threshold: This property can be used to define a region
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@ -657,6 +659,7 @@ Example:
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qcom,mdss-dsi-mdp-trigger = <0>;
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qcom,mdss-dsi-dma-trigger = <0>;
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qcom,mdss-dsi-panel-framerate = <60>;
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qcom,mdss-dsi-host-esc-clk-freq-hz = <19200000>;
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qcom,mdss-dsi-panel-clockrate = <424000000>;
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qcom,mdss-mdp-kickoff-threshold = <11 2430>;
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qcom,mdss-mdp-kickoff-delay = <1000>;
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@ -34,7 +34,6 @@
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#include "mdss_dsi_phy.h"
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#include "mdss_dba_utils.h"
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#define XO_CLK_RATE 19200000
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#define CMDLINE_DSI_CTL_NUM_STRING_LEN 2
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/* Master structure to hold all the information about the DSI/panel */
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@ -1871,7 +1870,7 @@ static void __mdss_dsi_dyn_refresh_config(
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static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata)
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{
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u32 esc_clk_rate = XO_CLK_RATE;
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u32 esc_clk_rate_hz;
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u32 pipe_delay, pipe_delay2 = 0, pll_delay;
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u32 hsync_period = 0;
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u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
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@ -1898,9 +1897,11 @@ static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata)
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pinfo = &pdata->panel_info;
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pd = &(pinfo->mipi.dsi_phy_db);
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pclk_to_esc_ratio = (ctrl_pdata->pclk_rate / esc_clk_rate);
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byte_to_esc_ratio = (ctrl_pdata->byte_clk_rate / esc_clk_rate);
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hr_bit_to_esc_ratio = ((ctrl_pdata->byte_clk_rate * 4) / esc_clk_rate);
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esc_clk_rate_hz = ctrl_pdata->esc_clk_rate_hz;
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pclk_to_esc_ratio = (ctrl_pdata->pclk_rate / esc_clk_rate_hz);
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byte_to_esc_ratio = (ctrl_pdata->byte_clk_rate / esc_clk_rate_hz);
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hr_bit_to_esc_ratio = ((ctrl_pdata->byte_clk_rate * 4) /
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esc_clk_rate_hz);
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hsync_period = mdss_panel_get_htotal(pinfo, true);
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pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
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@ -1922,7 +1923,7 @@ static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata)
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((pd->timing[4] >> 1) + 1)) / hr_bit_to_esc_ratio);
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/* 130 us pll delay recommended by h/w doc */
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pll_delay = ((130 * esc_clk_rate) / 1000000) * 2;
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pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2;
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MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PIPE_DELAY,
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pipe_delay);
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@ -3057,7 +3058,7 @@ static int mdss_dsi_set_clk_rates(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
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rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
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MDSS_DSI_LINK_ESC_CLK,
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19200000,
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ctrl_pdata->esc_clk_rate_hz,
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MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
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if (rc) {
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pr_err("%s: dsi_esc_clk - clk_set_rate failed\n",
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@ -4236,6 +4237,9 @@ int dsi_panel_device_register(struct platform_device *ctrl_pdev,
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pr_debug("%s: pclk=%d, bclk=%d\n", __func__,
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ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate);
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ctrl_pdata->esc_clk_rate_hz = pinfo->esc_clk_rate_hz;
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pr_debug("%s: esc clk=%d\n", __func__,
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ctrl_pdata->esc_clk_rate_hz);
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rc = mdss_dsi_get_dt_vreg_data(&ctrl_pdev->dev, pan_node,
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&ctrl_pdata->panel_power_data, DSI_PANEL_PM);
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@ -477,6 +477,7 @@ struct mdss_dsi_ctrl_pdata {
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u32 byte_clk_rate;
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u32 pclk_rate_bkp;
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u32 byte_clk_rate_bkp;
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u32 esc_clk_rate_hz;
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bool refresh_clk_rate; /* flag to recalculate clk_rate */
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struct dss_module_power panel_power_data;
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struct dss_module_power power_data[DSI_MAX_PM]; /* for 8x10 */
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@ -2819,6 +2819,13 @@ static int mdss_panel_parse_dt(struct device_node *np,
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MSM_DBA_CHIP_NAME_MAX_LEN);
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}
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rc = of_property_read_u32(np,
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"qcom,mdss-dsi-host-esc-clk-freq-hz",
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&pinfo->esc_clk_rate_hz);
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if (rc)
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pinfo->esc_clk_rate_hz = MDSS_DSI_MAX_ESC_CLK_RATE_HZ;
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pr_debug("%s: esc clk %d\n", __func__, pinfo->esc_clk_rate_hz);
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return 0;
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error:
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@ -29,6 +29,9 @@ struct panel_id {
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#define DEFAULT_FRAME_RATE 60
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#define DEFAULT_ROTATOR_FRAME_RATE 120
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#define ROTATOR_LOW_FRAME_RATE 30
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#define MDSS_DSI_MAX_ESC_CLK_RATE_HZ 19200000
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#define MDSS_DSI_RST_SEQ_LEN 10
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/* worst case prefill lines for all chipsets including all vertical blank */
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#define MDSS_MDP_MAX_PREFILL_FETCH 25
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@ -909,6 +912,9 @@ struct mdss_panel_info {
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/* HDR properties of display panel*/
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struct mdss_panel_hdr_properties hdr_properties;
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/* esc clk recommended for the panel */
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u32 esc_clk_rate_hz;
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};
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struct mdss_panel_timing {
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