Merge "power: qpnp-fg-gen3: configure ESR FCC based on Qnovo enable status"

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Linux Build Service Account 2017-04-26 06:33:50 -07:00 committed by Gerrit - the friendly Code Review server
commit 4d68ab6fd6

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@ -1970,7 +1970,7 @@ static int fg_esr_fcc_config(struct fg_chip *chip)
{
union power_supply_propval prop = {0, };
int rc;
bool parallel_en = false;
bool parallel_en = false, qnovo_en = false;
if (is_parallel_charger_available(chip)) {
rc = power_supply_get_property(chip->parallel_psy,
@ -1983,19 +1983,25 @@ static int fg_esr_fcc_config(struct fg_chip *chip)
parallel_en = prop.intval;
}
fg_dbg(chip, FG_POWER_SUPPLY, "charge_status: %d parallel_en: %d esr_fcc_ctrl_en: %d\n",
chip->charge_status, parallel_en, chip->esr_fcc_ctrl_en);
rc = power_supply_get_property(chip->batt_psy,
POWER_SUPPLY_PROP_CHARGE_QNOVO_ENABLE, &prop);
if (!rc)
qnovo_en = prop.intval;
fg_dbg(chip, FG_POWER_SUPPLY, "chg_sts: %d par_en: %d qnov_en: %d esr_fcc_ctrl_en: %d\n",
chip->charge_status, parallel_en, qnovo_en,
chip->esr_fcc_ctrl_en);
if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING &&
parallel_en) {
(parallel_en || qnovo_en)) {
if (chip->esr_fcc_ctrl_en)
return 0;
/*
* When parallel charging is enabled, configure ESR FCC to
* 300mA to trigger an ESR pulse. Without this, FG can ask
* the main charger to increase FCC when it is supposed to
* decrease it.
* When parallel charging or Qnovo is enabled, configure ESR
* FCC to 300mA to trigger an ESR pulse. Without this, FG can
* request the main charger to increase FCC when it is supposed
* to decrease it.
*/
rc = fg_masked_write(chip, BATT_INFO_ESR_FAST_CRG_CFG(chip),
ESR_FAST_CRG_IVAL_MASK |
@ -2014,8 +2020,8 @@ static int fg_esr_fcc_config(struct fg_chip *chip)
/*
* If we're here, then it means either the device is not in
* charging state or parallel charging is disabled. Disable
* ESR fast charge current control in SW.
* charging state or parallel charging / Qnovo is disabled.
* Disable ESR fast charge current control in SW.
*/
rc = fg_masked_write(chip, BATT_INFO_ESR_FAST_CRG_CFG(chip),
ESR_FAST_CRG_CTL_EN_BIT, 0);