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ARM: dts: mvebu: pl310-cache disable double-linefill

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commit cda80a82ac3e89309706c027ada6ab232be1d640 upstream.

Under heavy system stress mvebu SoC using Cortex A9 sporadically
encountered instability issues.

The "double linefill" feature of L2 cache was identified as causing
dependency between read and write which lead to the deadlock.

Especially, it was the cause of deadlock seen under heavy PCIe traffic,
as this dependency violates PCIE overtaking rule.

Fixes: c8f5a878e5 ("ARM: mvebu: use DT properties to fine-tune the L2 configuration")
Signed-off-by: Yan Markman <ymarkman@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
[gregory.clement@free-electrons.com: reformulate commit log, add Armada
375 and add Fixes tag]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Yan Markman 2016-10-16 00:22:32 +03:00 • committed by Greg Kroah-Hartman
parent 581ac5f431
commit 4e351b8dd8
3 changed files with 6 additions and 6 deletions
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4
arch/arm/boot/dts/armada-375.dtsi
View file

@ -176,9 +176,9 @@
reg = <0x8000 0x1000>; reg = <0x8000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>; arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>; arm,double-linefill = <0>;
prefetch-data = <1>; prefetch-data = <1>;
}; };

4
arch/arm/boot/dts/armada-38x.dtsi
View file

@ -143,9 +143,9 @@
reg = <0x8000 0x1000>; reg = <0x8000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>; arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>; arm,double-linefill = <0>;
prefetch-data = <1>; prefetch-data = <1>;
}; };

4
arch/arm/boot/dts/armada-39x.dtsi
View file

@ -104,9 +104,9 @@
reg = <0x8000 0x1000>; reg = <0x8000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,double-linefill-incr = <1>; arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>; arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>; arm,double-linefill = <0>;
prefetch-data = <1>; prefetch-data = <1>;
}; };