Merge "ARM: dts: msm: specify SPI configuration for msmfalcon."
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229
arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi
Normal file
229
arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi
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@ -0,0 +1,229 @@
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "msmfalcon-pinctrl.dtsi"
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/ {
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aliases {
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spi1 = &spi_1;
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spi2 = &spi_2;
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spi3 = &spi_3;
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spi4 = &spi_4;
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spi5 = &spi_5;
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spi6 = &spi_6;
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spi7 = &spi_7;
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spi8 = &spi_8;
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};
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};
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&soc {
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spi_1: spi@c175000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc175000 0x600>,
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<0xc144000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 95 0>, <0 238 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <4>;
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qcom,bam-producer-pipe-index = <5>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_1_active>;
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pinctrl-1 = <&spi_1_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_2: spi@c176000 { /* BLSP1 QUP2 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc176000 0x600>,
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<0xc144000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 96 0>, <0 238 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <6>;
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qcom,bam-producer-pipe-index = <7>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_2_active>;
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pinctrl-1 = <&spi_2_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_3: spi@c177000 { /* BLSP1 QUP3 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc177000 0x600>,
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<0xc144000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 97 0>, <0 238 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <8>;
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qcom,bam-producer-pipe-index = <9>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_3_active>;
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pinctrl-1 = <&spi_3_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_4: spi@c178000 { /* BLSP1 QUP4 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc178000 0x600>,
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<0xc144000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 98 0>, <0 238 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <10>;
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qcom,bam-producer-pipe-index = <11>;
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qcom,master-id = <86>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_4_active>;
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pinctrl-1 = <&spi_4_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
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<&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_5: spi@c1b5000 { /* BLSP2 QUP1 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc1b5000 0x600>,
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<0xc184000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 101 0>, <0 239 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <4>;
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qcom,bam-producer-pipe-index = <5>;
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qcom,master-id = <84>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_5_active>;
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pinctrl-1 = <&spi_5_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_6: spi@c1b6000 { /* BLSP2 QUP2 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc1b6000 0x600>,
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<0xc184000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 102 0>, <0 239 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <6>;
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qcom,bam-producer-pipe-index = <7>;
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qcom,master-id = <84>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_6_active>;
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pinctrl-1 = <&spi_6_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_7: spi@c1b7000 { /* BLSP2 QUP3 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc1b7000 0x600>,
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<0xc184000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 103 0>, <0 239 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <8>;
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qcom,bam-producer-pipe-index = <9>;
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qcom,master-id = <84>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_7_active>;
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pinctrl-1 = <&spi_7_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_8: spi@c1b8000 { /* BLSP2 QUP4 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0xc1b8000 0x600>,
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<0xc184000 0x1f000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 104 0>, <0 239 0>;
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spi-max-frequency = <50000000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <10>;
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qcom,bam-producer-pipe-index = <11>;
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qcom,master-id = <84>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_8_active>;
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pinctrl-1 = <&spi_8_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
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<&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>;
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status = "disabled";
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};
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};
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@ -112,5 +112,262 @@
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bias-pull-down; /* pull down */
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};
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};
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/* SPI CONFIGURATION */
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spi_1 {
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spi_1_active: spi_1_active {
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mux {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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function = "blsp_spi1";
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};
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config {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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spi_1_sleep: spi_1_sleep {
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mux {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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function = "blsp_spi1";
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};
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config {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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spi_2 {
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spi_2_active: spi_2_active {
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mux {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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function = "blsp_spi2";
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};
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config {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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drive-strength = <6>;
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bias-disable;
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};
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};
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spi_2_sleep: spi_2_sleep {
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mux {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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function = "blsp_spi2";
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};
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config {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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spi_3 {
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spi_3_active: spi_3_active {
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mux {
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pins = "gpio8", "gpio9",
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"gpio10", "gpio11";
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function = "blsp_spi3";
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};
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config {
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pins = "gpio8", "gpio9",
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"gpio10", "gpio11";
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drive-strength = <6>;
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bias-disable;
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};
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};
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spi_3_sleep: spi_3_sleep {
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mux {
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pins = "gpio8", "gpio9",
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"gpio10", "gpio11";
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function = "blsp_spi3";
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};
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config {
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pins = "gpio8", "gpio9",
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"gpio10", "gpio11";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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spi_4 {
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spi_4_active: spi_4_active {
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mux {
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pins = "gpio12", "gpio13",
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"gpio14", "gpio15";
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function = "blsp_spi4";
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};
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config {
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pins = "gpio12", "gpio13",
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"gpio14", "gpio15";
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drive-strength = <6>;
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bias-disable;
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};
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};
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spi_4_sleep: spi_4_sleep {
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mux {
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pins = "gpio12", "gpio13",
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"gpio14", "gpio15";
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function = "blsp_spi4";
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};
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config {
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pins = "gpio12", "gpio13",
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"gpio14", "gpio15";
|
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drive-strength = <6>;
|
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bias-disable;
|
||||
};
|
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};
|
||||
};
|
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spi_5 {
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spi_5_active: spi_5_active {
|
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mux {
|
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pins = "gpio16", "gpio17",
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"gpio18", "gpio19";
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function = "blsp_spi5";
|
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};
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config {
|
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pins = "gpio16", "gpio17",
|
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"gpio18", "gpio19";
|
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drive-strength = <6>;
|
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bias-disable;
|
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};
|
||||
};
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||||
|
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spi_5_sleep: spi_5_sleep {
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||||
mux {
|
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pins = "gpio16", "gpio17",
|
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"gpio18", "gpio19";
|
||||
function = "blsp_spi5";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio16", "gpio17",
|
||||
"gpio18", "gpio19";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi_6 {
|
||||
spi_6_active: spi_6_active {
|
||||
mux {
|
||||
pins = "gpio49", "gpio52",
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||||
"gpio22", "gpio23";
|
||||
function = "blsp_spi6";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio49", "gpio52",
|
||||
"gpio22", "gpio23";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_6_sleep: spi_6_sleep {
|
||||
mux {
|
||||
pins = "gpio49", "gpio52",
|
||||
"gpio22", "gpio23";
|
||||
function = "blsp_spi6";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio49", "gpio52",
|
||||
"gpio22", "gpio23";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi_7 {
|
||||
spi_7_active: spi_7_active {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio26", "gpio27";
|
||||
function = "blsp_spi7";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio26", "gpio27";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_7_sleep: spi_7_sleep {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio26", "gpio27";
|
||||
function = "blsp_spi7";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio26", "gpio27";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi_8 {
|
||||
spi_8_active: spi_8_active {
|
||||
mux {
|
||||
pins = "gpio28", "gpio29",
|
||||
"gpio30", "gpio31";
|
||||
function = "blsp_spi8";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio28", "gpio29",
|
||||
"gpio30", "gpio31";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_8_sleep: spi_8_sleep {
|
||||
mux {
|
||||
pins = "gpio28", "gpio29",
|
||||
"gpio30", "gpio31";
|
||||
function = "blsp_spi8";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio28", "gpio29",
|
||||
"gpio30", "gpio31";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -899,3 +899,4 @@
|
|||
#include "msm-pm2falcon.dtsi"
|
||||
#include "msm-arm-smmu-falcon.dtsi"
|
||||
#include "msm-arm-smmu-impl-defs-falcon.dtsi"
|
||||
#include "msmfalcon-blsp.dtsi"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue