msm: mdss: update mdp clock rate with pingpong split enabled
When pingpong split is enabled, single DSPP output is driving two interfaces and MDP clock has to be 2x times the pixel clock. In the current implementation, pingpong split is not considered in the MDP clock calculations. This change accounts for pingpong split and update MDP clock accordingly. Change-Id: I85a86fa747c908f76bd01faf36fe310d502e2121 Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> (cherry picked from commit 9aa39bfd928b40fa8f8b87b099dbb39d964be41f) [veeras@codeaurora.org: Resolve merge conflict in mdss_mdp_ctl.c] Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
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1 changed files with 9 additions and 4 deletions
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@ -832,10 +832,15 @@ static void mdss_mdp_perf_calc_mixer(struct mdss_mdp_mixer *mixer,
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perf->bw_writeback = apply_overhead_factors(
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perf->bw_writeback,
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true, false, fmt);
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} else if ((pinfo->type == MIPI_CMD_PANEL) &&
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(pinfo->mipi.dsi_pclk_rate > perf->mdp_clk_rate)) {
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/* for command mode, run as fast as the link allows */
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perf->mdp_clk_rate = pinfo->mipi.dsi_pclk_rate;
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/* for command mode, run as fast as the link allows us */
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} else if (pinfo->type == MIPI_CMD_PANEL) {
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u32 dsi_pclk_rate = pinfo->mipi.dsi_pclk_rate;
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if (is_pingpong_split(mixer->ctl->mfd))
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dsi_pclk_rate *= 2;
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if (dsi_pclk_rate > perf->mdp_clk_rate)
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perf->mdp_clk_rate = dsi_pclk_rate;
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}
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}
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