From 4f54b53642ee800232249c35c6dfd901a4ccd39c Mon Sep 17 00:00:00 2001
From: David Collins <collinsd@codeaurora.org>
Date: Mon, 4 Apr 2016 15:16:30 -0700
Subject: [PATCH] ARM: dts: msm: set VDD_APCC CPR IRQ affinity for CPU0/1 on
 msm8996pro

Set the CPR IRQ affinity of the VDD_APCC CPR3 controller to be
both cores of the APPS power cluster (i.e. CPU0 and CPU1).  This
ensures that neither of the CPU cores of the performance cluster
will be woken up to service a VDD_APCC CPR IRQ which was
generated when the last performance cluster core power collapsed.

Change-Id: I055e50ffcb85622ddd67d55b44d77c342e9ec074
CRs-Fixed: 949650
Signed-off-by: David Collins <collinsd@codeaurora.org>
---
 arch/arm/boot/dts/qcom/msm8996pro.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/qcom/msm8996pro.dtsi b/arch/arm/boot/dts/qcom/msm8996pro.dtsi
index 59ffa3ce88cb..a9933c038992 100644
--- a/arch/arm/boot/dts/qcom/msm8996pro.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996pro.dtsi
@@ -33,6 +33,7 @@
 
 &apcc_cpr {
 	compatible = "qcom,cpr3-msm8996pro-hmss-regulator";
+	qcom,cpr-interrupt-affinity = <&CPU0 &CPU1>;
 };
 
 &apc0_pwrcl_vreg {