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ARM: dts: msm: Add sdhc1 and sdhc2 for sdm630

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Add sdhc1 for enabling eMMC and sdhc2 for enabling SD card for sdm630
target. Since sdm660 and sdm630 have same entries for eMMC and SD card,
the common entires are added to sdm660-common.dtsi. If later on some
properties change, overwrite or use delete-property on those entries in
the appropriate DT files.

Change-Id: Ib43fb23a18e56f2d6d270598584ed8a8470c3d86
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
This commit is contained in:
Vijay Viswanath 2017-01-23 11:57:14 +05:30
parent 314869eb56
commit 4f92347754
5 changed files with 243 additions and 0 deletions
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49
arch/arm/boot/dts/qcom/sdm630-cdp.dtsi
View file

@ -26,3 +26,52 @@
&pm660_charger {
qcom,batteryless-platform;
};
&sdhc_1 {
/* device core power supply */
vdd-supply = <&pm660l_l4>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&pm660_l8>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <110 325000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
};
&sdhc_2 {
/* device core power supply */
vdd-supply = <&pm660l_l5>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <15000 800000>;
/* device communication power supply */
vdd-io-supply = <&pm660l_l2>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
#address-cells = <0>;
interrupt-parent = <&sdhc_2>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 125 0
1 &intc 0 0 221 0
2 &tlmm 54 0>;
interrupt-names = "hc_irq", "pwr_irq", "status_irq";
cd-gpios = <&tlmm 54 0x1>;
status = "ok";
};

49
arch/arm/boot/dts/qcom/sdm630-mtp.dtsi
View file

@ -35,3 +35,52 @@
&pm660_fg {
qcom,battery-data = <&mtp_batterydata>;
};
&sdhc_1 {
/* device core power supply */
vdd-supply = <&pm660l_l4>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&pm660_l8>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <110 325000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
};
&sdhc_2 {
/* device core power supply */
vdd-supply = <&pm660l_l5>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <15000 800000>;
/* device communication power supply */
vdd-io-supply = <&pm660l_l2>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
#address-cells = <0>;
interrupt-parent = <&sdhc_2>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 125 0
1 &intc 0 0 221 0
2 &tlmm 54 0>;
interrupt-names = "hc_irq", "pwr_irq", "status_irq";
cd-gpios = <&tlmm 54 0x1>;
status = "ok";
};

49
arch/arm/boot/dts/qcom/sdm630-rumi.dts
View file

@ -86,3 +86,52 @@
compatible = "qcom,dummycc";
clock-output-names = "debug_clocks";
};
&sdhc_1 {
/* device core power supply */
vdd-supply = <&pm660l_l4>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <200 570000>;
/* device communication power supply */
vdd-io-supply = <&pm660_l8>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <110 325000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
status = "ok";
};
&sdhc_2 {
/* device core power supply */
vdd-supply = <&pm660l_l5>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <15000 800000>;
/* device communication power supply */
vdd-io-supply = <&pm660l_l2>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 22000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
#address-cells = <0>;
interrupt-parent = <&sdhc_2>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 0 125 0
1 &intc 0 0 221 0
2 &tlmm 54 0>;
interrupt-names = "hc_irq", "pwr_irq", "status_irq";
cd-gpios = <&tlmm 54 0x1>;
status = "ok";
};

2
arch/arm/boot/dts/qcom/sdm630.dtsi
View file

@ -26,6 +26,8 @@
aliases {
serial0 = &uartblsp1dm1;
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
sdhc2 = &sdhc_2; /* SDC2 for SD card */
};
chosen {

94
arch/arm/boot/dts/qcom/sdm660-common.dtsi
View file

@ -321,4 +321,98 @@
reg = <0xa8f8000 0x300>;
qcom,reset-ep-after-lpm-resume;
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;
reg-names = "hc_mem", "cmdq_mem";
interrupts = <0 110 0>, <0 112 0>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <8>;
qcom,large-address-bus;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <26 81>;
qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
qcom,pm-qos-cmdq-latency-us = <26 81>, <26 81>;
qcom,pm-qos-legacy-latency-us = <26 81>, <26 81>;
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <9>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
<78 512 1046 3200>, /* 400 KB/s*/
<78 512 52286 160000>, /* 20 MB/s */
<78 512 65360 200000>, /* 25 MB/s */
<78 512 130718 400000>, /* 50 MB/s */
<78 512 130718 400000>, /* 100 MB/s */
<78 512 261438 800000>, /* 200 MB/s */
<78 512 261438 800000>, /* 400 MB/s */
<78 512 1338562 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 400000000 4294967295>;
clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
<&clock_gcc GCC_SDCC1_APPS_CLK>,
<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface_clk", "core_clk", "ice_core_clk";
qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
192000000 384000000>;
qcom,nonremovable;
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
qcom,ice-clk-rates = <300000000 150000000>;
status = "disabled";
};
sdhc_2: sdhci@c084000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc084000 0x1000>;
reg-names = "hc_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <4>;
qcom,large-address-bus;
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
<81 512 1046 3200>, /* 400 KB/s */
<81 512 52286 160000>, /* 20 MB/s */
<81 512 65360 200000>, /* 25 MB/s */
<81 512 130718 400000>, /* 50 MB/s */
<81 512 261438 800000>, /* 100 MB/s */
<81 512 261438 800000>, /* 200 MB/s */
<81 512 1338562 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 4294967295>;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <26 81>;
qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
qcom,pm-qos-legacy-latency-us = <26 81>, <26 81>;
clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
<&clock_gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface_clk", "core_clk";
qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
200000000>;
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
"SDR104";
status = "disabled";
};
};