clk: msm: clock-osm: Add measurement support for CPU clocks

Add support to measure the perf and power cluster clocks
via the debug mux on MSMCOBALT.

CRs-Fixed: 1059153
Change-Id: I1682481dfe22deef300ea9bd1db558ae634c9129
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

Documentation/devicetree/bindings/arm/msm/qcom,osm.txt

@@ -22,7 +22,7 @@ Properties:
 	Usage:      required
 	Value type: <stringlist>
 	Definition: Address names. Must be "osm", "pwrcl_pll", "perfcl_pll",
-		    and "apcs_common". Optionally, "pwrcl_efuse" or
+		    "apcs_common" and "debug". Optionally, "pwrcl_efuse" or
 		    "perfcl_efuse".
 		    Must be specified in the same order as the corresponding
 		    addresses are specified in the reg property.
@@ -303,9 +303,10 @@ Example:
 		reg = <0x179C0000 0x4000>,
 		      <0x17916000 0x1000>,
 		      <0x17816000 0x1000>,
-		      <0x179D1000 0x1000>;
+		      <0x179D1000 0x1000>,
+		      <0x1791101c 0x8>;
 		reg-names = "osm", "pwrcl_pll", "perfcl_pll",
-			    "apcs_common";
+			    "apcs_common", "debug";
 
 		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
 		vdd-perfcl-supply = <&apc1_perfcl_vreg>;

arch/arm/boot/dts/qcom/msmcobalt.dtsi

@@ -806,9 +806,10 @@
 		      <0x17916000 0x1000>,
 		      <0x17816000 0x1000>,
 		      <0x179d1000 0x1000>,
-		      <0x00784130 0x8>;
+		      <0x00784130 0x8>,
+		      <0x1791101c 0x8>;
 		reg-names = "osm", "pwrcl_pll", "perfcl_pll",
-			    "apcs_common", "perfcl_efuse";
+			    "apcs_common", "perfcl_efuse", "debug";
 
 		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
 		vdd-perfcl-supply = <&apc1_perfcl_vreg>;
@@ -941,10 +942,11 @@
 		reg = <0x162000 0x4>;
 		reg-names = "cc_base";
 		clock-names = "debug_gpu_clk", "debug_gfx_clk",
-				"debug_mmss_clk";
+				"debug_mmss_clk", "debug_cpu_clk";
 		clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>,
 			 <&clock_gfx clk_gfxcc_dbg_clk>,
-			 <&clock_mmss clk_mmss_debug_mux>;
+			 <&clock_mmss clk_mmss_debug_mux>,
+			 <&clock_cpu clk_cpu_debug_mux>;
 		#clock-cells = <1>;
 	};
 

drivers/clk/msm/clock-gcc-cobalt.c

@@ -2353,11 +2353,13 @@ static struct mux_clk gcc_debug_mux = {
 		&gpu_gcc_debug_clk.c,
 		&gfx_gcc_debug_clk.c,
 		&debug_mmss_clk.c,
+		&debug_cpu_clk.c,
 	),
 	MUX_SRC_LIST(
 		{ &gpu_gcc_debug_clk.c, 0x013d },
 		{ &gfx_gcc_debug_clk.c, 0x013d },
 		{ &debug_mmss_clk.c, 0x0022 },
+		{ &debug_cpu_clk.c, 0x00c0 },
 		{ &snoc_clk.c, 0x0000 },
 		{ &cnoc_clk.c, 0x000e },
 		{ &bimc_clk.c, 0x00a9 },
@@ -2831,6 +2833,7 @@ static struct clk_lookup msm_clocks_measure_cobalt[] = {
 	CLK_LIST(gpu_gcc_debug_clk),
 	CLK_LIST(gfx_gcc_debug_clk),
 	CLK_LIST(debug_mmss_clk),
+	CLK_LIST(debug_cpu_clk),
 	CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
 };
 
@@ -2867,6 +2870,9 @@ static int msm_clock_debug_cobalt_probe(struct platform_device *pdev)
 	debug_mmss_clk.dev = &pdev->dev;
 	debug_mmss_clk.clk_id = "debug_mmss_clk";
 
+	debug_cpu_clk.dev = &pdev->dev;
+	debug_cpu_clk.clk_id = "debug_cpu_clk";
+
 	ret = of_msm_clock_register(pdev->dev.of_node,
 				    msm_clocks_measure_cobalt,
 				    ARRAY_SIZE(msm_clocks_measure_cobalt));

drivers/clk/msm/clock-osm.c

@@ -215,6 +215,7 @@ enum clk_osm_trace_packet_id {
 #define PERFCL_EFUSE_MASK	0x7
 
 static void __iomem *virt_base;
+static void __iomem *debug_base;
 
 #define lmh_lite_clk_src_source_val 1
 
@@ -531,14 +532,45 @@ static struct clk_osm perfcl_clk = {
 	},
 };
 
+static struct clk_ops clk_ops_cpu_dbg_mux;
+
+static struct mux_clk cpu_debug_mux = {
+	.offset = 0x0,
+	.mask = 0x3,
+	.shift = 8,
+	.ops = &mux_reg_ops,
+	MUX_SRC_LIST(
+		{ &pwrcl_clk.c, 0x00 },
+		{ &perfcl_clk.c, 0x01 },
+	),
+	.base = &debug_base,
+	.c = {
+		.dbg_name = "cpu_debug_mux",
+		.ops = &clk_ops_cpu_dbg_mux,
+		.flags = CLKFLAG_NO_RATE_CACHE,
+		CLK_INIT(cpu_debug_mux.c),
+	},
+};
+
 static struct clk_lookup cpu_clocks_osm[] = {
 	CLK_LIST(pwrcl_clk),
 	CLK_LIST(perfcl_clk),
 	CLK_LIST(sys_apcsaux_clk_gcc),
 	CLK_LIST(xo_ao),
 	CLK_LIST(osm_clk_src),
+	CLK_LIST(cpu_debug_mux),
 };
 
+static unsigned long cpu_dbg_mux_get_rate(struct clk *clk)
+{
+	/* Account for the divider between the clock and the debug mux */
+	if (!strcmp(clk->parent->dbg_name, "pwrcl_clk"))
+		return clk->rate/4;
+	else if (!strcmp(clk->parent->dbg_name, "perfcl_clk"))
+		return clk->rate/8;
+	return clk->rate;
+}
+
 static void clk_osm_print_osm_table(struct clk_osm *c)
 {
 	int i;
@@ -907,6 +939,22 @@ static int clk_osm_resources_init(struct platform_device *pdev)
 		}
 	}
 
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "debug");
+	if (!res) {
+		dev_err(&pdev->dev, "Failed to get debug mux base\n");
+		return -EINVAL;
+	}
+
+	debug_base = devm_ioremap(&pdev->dev, res->start,
+						  resource_size(res));
+	if (!debug_base) {
+		dev_err(&pdev->dev, "Unable to map in debug mux base\n");
+		return -ENOMEM;
+	}
+
+	clk_ops_cpu_dbg_mux = clk_ops_gen_mux;
+	clk_ops_cpu_dbg_mux.get_rate = cpu_dbg_mux_get_rate;
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs_common");
 	if (!res) {
 		dev_err(&pdev->dev, "Failed to get apcs common base\n");

include/dt-bindings/clock/msm-clocks-cobalt.h

@@ -494,6 +494,7 @@
 #define clk_sys_apcsaux_clk_gcc			0xf905e862
 #define clk_xo_ao				0x428c856d
 #define clk_osm_clk_src				0xaabe68c3
+#define clk_cpu_debug_mux			0x3ae8bcb2
 
 /* Audio External Clocks */
 #define clk_audio_ap_clk			0x9b5727cb