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clk: berlin: add cpuclk

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Add cpuclk in the Berlin BG2Q clock driver. This clk has a divider
fixed to 1.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This commit is contained in:
Antoine Tenart 2015-10-15 20:55:55 +02:00 • committed by Sebastian Hesselbarth
parent 0f0ebb1349
commit 515f1a2027
1 changed files with 7 additions and 7 deletions
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14
drivers/clk/berlin/bg2q.c
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@ -45,7 +45,7 @@
#define REG_SDIO0XIN_CLKCTL 0x0158 #define REG_SDIO0XIN_CLKCTL 0x0158
#define REG_SDIO1XIN_CLKCTL 0x015c #define REG_SDIO1XIN_CLKCTL 0x015c
#define MAX_CLKS 27 #define MAX_CLKS 28
static struct clk *clks[MAX_CLKS]; static struct clk *clks[MAX_CLKS];
static struct clk_onecell_data clk_data; static struct clk_onecell_data clk_data;
static DEFINE_SPINLOCK(lock); static DEFINE_SPINLOCK(lock);
@ -356,13 +356,13 @@ static void __init berlin2q_clock_setup(struct device_node *np)
gd->bit_idx, 0, &lock); gd->bit_idx, 0, &lock);
} }
/* /* cpuclk divider is fixed to 1 */
* twdclk is derived from cpu/3 clks[CLKID_CPU] =
* TODO: use cpupll until cpuclk is not available clk_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],
*/ 0, 1, 1);
/* twdclk is derived from cpu/3 */
clks[CLKID_TWD] = clks[CLKID_TWD] =
clk_register_fixed_factor(NULL, "twd", clk_names[CPUPLL], clk_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
0, 1, 3);
/* check for errors on leaf clocks */ /* check for errors on leaf clocks */
for (n = 0; n < MAX_CLKS; n++) { for (n = 0; n < MAX_CLKS; n++) {