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Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

Browse source 
* 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, UV: uv_irq.c: Fix all sparse warnings
  x86, UV: Improve BAU performance and error recovery
  x86, UV: Delete unneeded boot messages
  x86, UV: Clean up UV headers for MMR definitions
This commit is contained in:
Linus Torvalds 2010-05-18 09:46:35 -07:00
commit 537b60d178
6 changed files with 1176 additions and 914 deletions
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243
arch/x86/include/asm/uv/uv_bau.h
View file

@ -27,13 +27,14 @@
* set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on. * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
* *
* We will use 31 sets, one for sending BAU messages from each of the 32 * We will use 31 sets, one for sending BAU messages from each of the 32
* cpu's on the node. * cpu's on the uvhub.
* *
* TLB shootdown will use the first of the 8 descriptors of each set. * TLB shootdown will use the first of the 8 descriptors of each set.
* Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set). * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
*/ */
#define UV_ITEMS_PER_DESCRIPTOR 8 #define UV_ITEMS_PER_DESCRIPTOR 8
#define MAX_BAU_CONCURRENT 3
#define UV_CPUS_PER_ACT_STATUS 32 #define UV_CPUS_PER_ACT_STATUS 32
#define UV_ACT_STATUS_MASK 0x3 #define UV_ACT_STATUS_MASK 0x3
#define UV_ACT_STATUS_SIZE 2 #define UV_ACT_STATUS_SIZE 2
@ -45,6 +46,9 @@
#define UV_PAYLOADQ_PNODE_SHIFT 49 #define UV_PAYLOADQ_PNODE_SHIFT 49
#define UV_PTC_BASENAME "sgi_uv/ptc_statistics" #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask)) #define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
#define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15
#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16
#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x000000000bUL
/* /*
* bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
@ -55,15 +59,29 @@
#define DESC_STATUS_SOURCE_TIMEOUT 3 #define DESC_STATUS_SOURCE_TIMEOUT 3
/* /*
* source side thresholds at which message retries print a warning * source side threshholds at which message retries print a warning
*/ */
#define SOURCE_TIMEOUT_LIMIT 20 #define SOURCE_TIMEOUT_LIMIT 20
#define DESTINATION_TIMEOUT_LIMIT 20 #define DESTINATION_TIMEOUT_LIMIT 20
/*
* misc. delays, in microseconds
*/
#define THROTTLE_DELAY 10
#define TIMEOUT_DELAY 10
#define BIOS_TO 1000
/* BIOS is assumed to set the destination timeout to 1003520 nanoseconds */
/*
* threshholds at which to use IPI to free resources
*/
#define PLUGSB4RESET 100
#define TIMEOUTSB4RESET 100
/* /*
* number of entries in the destination side payload queue * number of entries in the destination side payload queue
*/ */
#define DEST_Q_SIZE 17 #define DEST_Q_SIZE 20
/* /*
* number of destination side software ack resources * number of destination side software ack resources
*/ */
@ -72,9 +90,10 @@
/* /*
* completion statuses for sending a TLB flush message * completion statuses for sending a TLB flush message
*/ */
#define FLUSH_RETRY 1 #define FLUSH_RETRY_PLUGGED 1
#define FLUSH_GIVEUP 2 #define FLUSH_RETRY_TIMEOUT 2
#define FLUSH_COMPLETE 3 #define FLUSH_GIVEUP 3
#define FLUSH_COMPLETE 4
/* /*
* Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor) * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
@ -86,14 +105,14 @@
* 'base_dest_nodeid' field of the header corresponds to the * 'base_dest_nodeid' field of the header corresponds to the
* destination nodeID associated with that specified bit. * destination nodeID associated with that specified bit.
*/ */
struct bau_target_nodemask { struct bau_target_uvhubmask {
unsigned long bits[BITS_TO_LONGS(256)]; unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
}; };
/* /*
* mask of cpu's on a node * mask of cpu's on a uvhub
* (during initialization we need to check that unsigned long has * (during initialization we need to check that unsigned long has
* enough bits for max. cpu's per node) * enough bits for max. cpu's per uvhub)
*/ */
struct bau_local_cpumask { struct bau_local_cpumask {
unsigned long bits; unsigned long bits;
@ -135,8 +154,8 @@ struct bau_msg_payload {
struct bau_msg_header { struct bau_msg_header {
unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */ unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
/* bits 5:0 */ /* bits 5:0 */
unsigned int base_dest_nodeid:15; /* nasid>>1 (pnode) of */ unsigned int base_dest_nodeid:15; /* nasid (pnode<<1) of */
/* bits 20:6 */ /* first bit in node_map */ /* bits 20:6 */ /* first bit in uvhub map */
unsigned int command:8; /* message type */ unsigned int command:8; /* message type */
/* bits 28:21 */ /* bits 28:21 */
/* 0x38: SN3net EndPoint Message */ /* 0x38: SN3net EndPoint Message */
@ -146,26 +165,38 @@ struct bau_msg_header {
unsigned int rsvd_2:9; /* must be zero */ unsigned int rsvd_2:9; /* must be zero */
/* bits 40:32 */ /* bits 40:32 */
/* Suppl_A is 56-41 */ /* Suppl_A is 56-41 */
unsigned int payload_2a:8;/* becomes byte 16 of msg */ unsigned int sequence:16;/* message sequence number */
/* bits 48:41 */ /* not currently using */ /* bits 56:41 */ /* becomes bytes 16-17 of msg */
unsigned int payload_2b:8;/* becomes byte 17 of msg */
/* bits 56:49 */ /* not currently using */
/* Address field (96:57) is never used as an /* Address field (96:57) is never used as an
address (these are address bits 42:3) */ address (these are address bits 42:3) */
unsigned int rsvd_3:1; /* must be zero */ unsigned int rsvd_3:1; /* must be zero */
/* bit 57 */ /* bit 57 */
/* address bits 27:4 are payload */ /* address bits 27:4 are payload */
/* these 24 bits become bytes 12-14 of msg */ /* these next 24 (58-81) bits become bytes 12-14 of msg */
/* bits 65:58 land in byte 12 */
unsigned int replied_to:1;/* sent as 0 by the source to byte 12 */ unsigned int replied_to:1;/* sent as 0 by the source to byte 12 */
/* bit 58 */ /* bit 58 */
unsigned int msg_type:3; /* software type of the message*/
/* bits 61:59 */
unsigned int canceled:1; /* message canceled, resource to be freed*/
/* bit 62 */
unsigned int payload_1a:1;/* not currently used */
/* bit 63 */
unsigned int payload_1b:2;/* not currently used */
/* bits 65:64 */
unsigned int payload_1a:5;/* not currently used */ /* bits 73:66 land in byte 13 */
/* bits 63:59 */ unsigned int payload_1ca:6;/* not currently used */
unsigned int payload_1b:8;/* not currently used */ /* bits 71:66 */
/* bits 71:64 */ unsigned int payload_1c:2;/* not currently used */
unsigned int payload_1c:8;/* not currently used */ /* bits 73:72 */
/* bits 79:72 */
unsigned int payload_1d:2;/* not currently used */ /* bits 81:74 land in byte 14 */
unsigned int payload_1d:6;/* not currently used */
/* bits 79:74 */
unsigned int payload_1e:2;/* not currently used */
/* bits 81:80 */ /* bits 81:80 */
unsigned int rsvd_4:7; /* must be zero */ unsigned int rsvd_4:7; /* must be zero */
@ -178,7 +209,7 @@ struct bau_msg_header {
/* bits 95:90 */ /* bits 95:90 */
unsigned int rsvd_6:5; /* must be zero */ unsigned int rsvd_6:5; /* must be zero */
/* bits 100:96 */ /* bits 100:96 */
unsigned int int_both:1;/* if 1, interrupt both sockets on the blade */ unsigned int int_both:1;/* if 1, interrupt both sockets on the uvhub */
/* bit 101*/ /* bit 101*/
unsigned int fairness:3;/* usually zero */ unsigned int fairness:3;/* usually zero */
/* bits 104:102 */ /* bits 104:102 */
@ -191,13 +222,18 @@ struct bau_msg_header {
/* bits 127:107 */ /* bits 127:107 */
}; };
/* see msg_type: */
#define MSG_NOOP 0
#define MSG_REGULAR 1
#define MSG_RETRY 2
/* /*
* The activation descriptor: * The activation descriptor:
* The format of the message to send, plus all accompanying control * The format of the message to send, plus all accompanying control
* Should be 64 bytes * Should be 64 bytes
*/ */
struct bau_desc { struct bau_desc {
struct bau_target_nodemask distribution; struct bau_target_uvhubmask distribution;
/* /*
* message template, consisting of header and payload: * message template, consisting of header and payload:
*/ */
@ -237,19 +273,25 @@ struct bau_payload_queue_entry {
unsigned short acknowledge_count; /* filled in by destination */ unsigned short acknowledge_count; /* filled in by destination */
/* 16 bits, bytes 10-11 */ /* 16 bits, bytes 10-11 */
/* these next 3 bytes come from bits 58-81 of the message header */
unsigned short replied_to:1; /* sent as 0 by the source */ unsigned short replied_to:1; /* sent as 0 by the source */
/* 1 bit */ unsigned short msg_type:3; /* software message type */
unsigned short unused1:7; /* not currently using */ unsigned short canceled:1; /* sent as 0 by the source */
/* 7 bits: byte 12) */ unsigned short unused1:3; /* not currently using */
/* byte 12 */
unsigned char unused2[2]; /* not currently using */ unsigned char unused2a; /* not currently using */
/* bytes 13-14 */ /* byte 13 */
unsigned char unused2; /* not currently using */
/* byte 14 */
unsigned char sw_ack_vector; /* filled in by the hardware */ unsigned char sw_ack_vector; /* filled in by the hardware */
/* byte 15 (bits 127:120) */ /* byte 15 (bits 127:120) */
unsigned char unused4[3]; /* not currently using bytes 17-19 */ unsigned short sequence; /* message sequence number */
/* bytes 17-19 */ /* bytes 16-17 */
unsigned char unused4[2]; /* not currently using bytes 18-19 */
/* bytes 18-19 */
int number_of_cpus; /* filled in at destination */ int number_of_cpus; /* filled in at destination */
/* 32 bits, bytes 20-23 (aligned) */ /* 32 bits, bytes 20-23 (aligned) */
@ -259,63 +301,93 @@ struct bau_payload_queue_entry {
}; };
/* /*
* one for every slot in the destination payload queue * one per-cpu; to locate the software tables
*/
struct bau_msg_status {
struct bau_local_cpumask seen_by; /* map of cpu's */
};
/*
* one for every slot in the destination software ack resources
*/
struct bau_sw_ack_status {
struct bau_payload_queue_entry *msg; /* associated message */
int watcher; /* cpu monitoring, or -1 */
};
/*
* one on every node and per-cpu; to locate the software tables
*/ */
struct bau_control { struct bau_control {
struct bau_desc *descriptor_base; struct bau_desc *descriptor_base;
struct bau_payload_queue_entry *bau_msg_head;
struct bau_payload_queue_entry *va_queue_first; struct bau_payload_queue_entry *va_queue_first;
struct bau_payload_queue_entry *va_queue_last; struct bau_payload_queue_entry *va_queue_last;
struct bau_msg_status *msg_statuses; struct bau_payload_queue_entry *bau_msg_head;
int *watching; /* pointer to array */ struct bau_control *uvhub_master;
struct bau_control *socket_master;
unsigned long timeout_interval;
atomic_t active_descriptor_count;
int max_concurrent;
int max_concurrent_constant;
int retry_message_scans;
int plugged_tries;
int timeout_tries;
int ipi_attempts;
int conseccompletes;
short cpu;
short uvhub_cpu;
short uvhub;
short cpus_in_socket;
short cpus_in_uvhub;
unsigned short message_number;
unsigned short uvhub_quiesce;
short socket_acknowledge_count[DEST_Q_SIZE];
cycles_t send_message;
spinlock_t masks_lock;
spinlock_t uvhub_lock;
spinlock_t queue_lock;
}; };
/* /*
* This structure is allocated per_cpu for UV TLB shootdown statistics. * This structure is allocated per_cpu for UV TLB shootdown statistics.
*/ */
struct ptc_stats { struct ptc_stats {
unsigned long ptc_i; /* number of IPI-style flushes */ /* sender statistics */
unsigned long requestor; /* number of nodes this cpu sent to */ unsigned long s_giveup; /* number of fall backs to IPI-style flushes */
unsigned long requestee; /* times cpu was remotely requested */ unsigned long s_requestor; /* number of shootdown requests */
unsigned long alltlb; /* times all tlb's on this cpu were flushed */ unsigned long s_stimeout; /* source side timeouts */
unsigned long onetlb; /* times just one tlb on this cpu was flushed */ unsigned long s_dtimeout; /* destination side timeouts */
unsigned long s_retry; /* retries on source side timeouts */ unsigned long s_time; /* time spent in sending side */
unsigned long d_retry; /* retries on destination side timeouts */ unsigned long s_retriesok; /* successful retries */
unsigned long sflush; /* cycles spent in uv_flush_tlb_others */ unsigned long s_ntargcpu; /* number of cpus targeted */
unsigned long dflush; /* cycles spent on destination side */ unsigned long s_ntarguvhub; /* number of uvhubs targeted */
unsigned long retriesok; /* successes on retries */ unsigned long s_ntarguvhub16; /* number of times >= 16 target hubs */
unsigned long nomsg; /* interrupts with no message */ unsigned long s_ntarguvhub8; /* number of times >= 8 target hubs */
unsigned long multmsg; /* interrupts with multiple messages */ unsigned long s_ntarguvhub4; /* number of times >= 4 target hubs */
unsigned long ntargeted;/* nodes targeted */ unsigned long s_ntarguvhub2; /* number of times >= 2 target hubs */
unsigned long s_ntarguvhub1; /* number of times == 1 target hub */
unsigned long s_resets_plug; /* ipi-style resets from plug state */
unsigned long s_resets_timeout; /* ipi-style resets from timeouts */
unsigned long s_busy; /* status stayed busy past s/w timer */
unsigned long s_throttles; /* waits in throttle */
unsigned long s_retry_messages; /* retry broadcasts */
/* destination statistics */
unsigned long d_alltlb; /* times all tlb's on this cpu were flushed */
unsigned long d_onetlb; /* times just one tlb on this cpu was flushed */
unsigned long d_multmsg; /* interrupts with multiple messages */
unsigned long d_nomsg; /* interrupts with no message */
unsigned long d_time; /* time spent on destination side */
unsigned long d_requestee; /* number of messages processed */
unsigned long d_retries; /* number of retry messages processed */
unsigned long d_canceled; /* number of messages canceled by retries */
unsigned long d_nocanceled; /* retries that found nothing to cancel */
unsigned long d_resets; /* number of ipi-style requests processed */
unsigned long d_rcanceled; /* number of messages canceled by resets */
}; };
static inline int bau_node_isset(int node, struct bau_target_nodemask *dstp) static inline int bau_uvhub_isset(int uvhub, struct bau_target_uvhubmask *dstp)
{ {
return constant_test_bit(node, &dstp->bits[0]); return constant_test_bit(uvhub, &dstp->bits[0]);
} }
static inline void bau_node_set(int node, struct bau_target_nodemask *dstp) static inline void bau_uvhub_set(int uvhub, struct bau_target_uvhubmask *dstp)
{ {
__set_bit(node, &dstp->bits[0]); __set_bit(uvhub, &dstp->bits[0]);
} }
static inline void bau_nodes_clear(struct bau_target_nodemask *dstp, int nbits) static inline void bau_uvhubs_clear(struct bau_target_uvhubmask *dstp,
int nbits)
{ {
bitmap_zero(&dstp->bits[0], nbits); bitmap_zero(&dstp->bits[0], nbits);
} }
static inline int bau_uvhub_weight(struct bau_target_uvhubmask *dstp)
{
return bitmap_weight((unsigned long *)&dstp->bits[0],
UV_DISTRIBUTION_SIZE);
}
static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits) static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
{ {
@ -328,4 +400,35 @@ static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
extern void uv_bau_message_intr1(void); extern void uv_bau_message_intr1(void);
extern void uv_bau_timeout_intr1(void); extern void uv_bau_timeout_intr1(void);
struct atomic_short {
short counter;
};
/**
* atomic_read_short - read a short atomic variable
* @v: pointer of type atomic_short
*
* Atomically reads the value of @v.
*/
static inline int atomic_read_short(const struct atomic_short *v)
{
return v->counter;
}
/**
* atomic_add_short_return - add and return a short int
* @i: short value to add
* @v: pointer of type atomic_short
*
* Atomically adds @i to @v and returns @i + @v
*/
static inline int atomic_add_short_return(short i, struct atomic_short *v)
{
short __i = i;
asm volatile(LOCK_PREFIX "xaddw %0, %1"
: "+r" (i), "+m" (v->counter)
: : "memory");
return i + __i;
}
#endif /* _ASM_X86_UV_UV_BAU_H */ #endif /* _ASM_X86_UV_UV_BAU_H */

2
arch/x86/include/asm/uv/uv_hub.h
View file

@ -307,7 +307,7 @@ static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset
* Access Global MMR space using the MMR space located at the top of physical * Access Global MMR space using the MMR space located at the top of physical
* memory. * memory.
*/ */
static inline unsigned long *uv_global_mmr64_address(int pnode, unsigned long offset) static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
{ {
return __va(UV_GLOBAL_MMR64_BASE | return __va(UV_GLOBAL_MMR64_BASE |
UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);

528
arch/x86/include/asm/uv/uv_mmrs.h
View file

@ -1,4 +1,3 @@
/* /*
* This file is subject to the terms and conditions of the GNU General Public * This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive * License. See the file "COPYING" in the main directory of this archive
@ -14,14 +13,26 @@
#define UV_MMR_ENABLE (1UL << 63) #define UV_MMR_ENABLE (1UL << 63)
/* ========================================================================= */
/* UVH_BAU_DATA_BROADCAST */
/* ========================================================================= */
#define UVH_BAU_DATA_BROADCAST 0x61688UL
#define UVH_BAU_DATA_BROADCAST_32 0x0440
#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
union uvh_bau_data_broadcast_u {
unsigned long v;
struct uvh_bau_data_broadcast_s {
unsigned long enable : 1; /* RW */
unsigned long rsvd_1_63: 63; /* */
} s;
};
/* ========================================================================= */ /* ========================================================================= */
/* UVH_BAU_DATA_CONFIG */ /* UVH_BAU_DATA_CONFIG */
/* ========================================================================= */ /* ========================================================================= */
#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
#define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15
#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16
#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x000000000bUL
/* 1011 timebase 7 (168millisec) * 3 ticks -> 500ms */
#define UVH_BAU_DATA_CONFIG 0x61680UL #define UVH_BAU_DATA_CONFIG 0x61680UL
#define UVH_BAU_DATA_CONFIG_32 0x0438 #define UVH_BAU_DATA_CONFIG_32 0x0438
@ -603,6 +614,68 @@ union uvh_lb_bau_intd_software_acknowledge_u {
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70
/* ========================================================================= */
/* UVH_LB_BAU_MISC_CONTROL */
/* ========================================================================= */
#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
#define UVH_LB_BAU_MISC_CONTROL_32 0x00a10
#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_SHFT 11
#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
#define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48
#define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
union uvh_lb_bau_misc_control_u {
unsigned long v;
struct uvh_lb_bau_misc_control_s {
unsigned long rejection_delay : 8; /* RW */
unsigned long apic_mode : 1; /* RW */
unsigned long force_broadcast : 1; /* RW */
unsigned long force_lock_nop : 1; /* RW */
unsigned long csi_agent_presence_vector : 3; /* RW */
unsigned long descriptor_fetch_mode : 1; /* RW */
unsigned long enable_intd_soft_ack_mode : 1; /* RW */
unsigned long intd_soft_ack_timeout_period : 4; /* RW */
unsigned long enable_dual_mapping_mode : 1; /* RW */
unsigned long vga_io_port_decode_enable : 1; /* RW */
unsigned long vga_io_port_16_bit_decode : 1; /* RW */
unsigned long suppress_dest_registration : 1; /* RW */
unsigned long programmed_initial_priority : 3; /* RW */
unsigned long use_incoming_priority : 1; /* RW */
unsigned long enable_programmed_initial_priority : 1; /* RW */
unsigned long rsvd_29_47 : 19; /* */
unsigned long fun : 16; /* RW */
} s;
};
/* ========================================================================= */ /* ========================================================================= */
/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
/* ========================================================================= */ /* ========================================================================= */
@ -680,334 +753,6 @@ union uvh_lb_bau_sb_descriptor_base_u {
} s; } s;
}; };
/* ========================================================================= */
/* UVH_LB_MCAST_AOERR0_RPT_ENABLE */
/* ========================================================================= */
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42
#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL
union uvh_lb_mcast_aoerr0_rpt_enable_u {
unsigned long v;
struct uvh_lb_mcast_aoerr0_rpt_enable_s {
unsigned long mcast_obese_msg : 1; /* RW */
unsigned long mcast_data_sb_err : 1; /* RW */
unsigned long mcast_nack_buff_parity : 1; /* RW */
unsigned long mcast_timeout : 1; /* RW */
unsigned long mcast_inactive_reply : 1; /* RW */
unsigned long mcast_upgrade_error : 1; /* RW */
unsigned long mcast_reg_count_underflow : 1; /* RW */
unsigned long mcast_rep_obese_msg : 1; /* RW */
unsigned long ucache_req_runt_msg : 1; /* RW */
unsigned long ucache_req_obese_msg : 1; /* RW */
unsigned long ucache_req_data_sb_err : 1; /* RW */
unsigned long ucache_rep_runt_msg : 1; /* RW */
unsigned long ucache_rep_obese_msg : 1; /* RW */
unsigned long ucache_rep_data_sb_err : 1; /* RW */
unsigned long ucache_rep_command_err : 1; /* RW */
unsigned long ucache_pend_timeout : 1; /* RW */
unsigned long macc_req_runt_msg : 1; /* RW */
unsigned long macc_req_obese_msg : 1; /* RW */
unsigned long macc_req_data_sb_err : 1; /* RW */
unsigned long macc_rep_runt_msg : 1; /* RW */
unsigned long macc_rep_obese_msg : 1; /* RW */
unsigned long macc_rep_data_sb_err : 1; /* RW */
unsigned long macc_amo_timeout : 1; /* RW */
unsigned long macc_put_timeout : 1; /* RW */
unsigned long macc_spurious_event : 1; /* RW */
unsigned long ioh_destination_table_parity : 1; /* RW */
unsigned long get_had_error_reply : 1; /* RW */
unsigned long get_timeout : 1; /* RW */
unsigned long lock_manager_had_error_reply : 1; /* RW */
unsigned long put_had_error_reply : 1; /* RW */
unsigned long put_timeout : 1; /* RW */
unsigned long sb_activation_overrun : 1; /* RW */
unsigned long completed_gb_activation_had_error_reply : 1; /* RW */
unsigned long completed_gb_activation_timeout : 1; /* RW */
unsigned long descriptor_buffer_0_parity : 1; /* RW */
unsigned long descriptor_buffer_1_parity : 1; /* RW */
unsigned long socket_destination_table_parity : 1; /* RW */
unsigned long bau_reply_payload_corruption : 1; /* RW */
unsigned long io_port_destination_table_parity : 1; /* RW */
unsigned long intd_soft_ack_timeout : 1; /* RW */
unsigned long int_rep_obese_msg : 1; /* RW */
unsigned long int_rep_command_err : 1; /* RW */
unsigned long int_timeout : 1; /* RW */
unsigned long rsvd_43_63 : 21; /* */
} s;
};
/* ========================================================================= */
/* UVH_LOCAL_INT0_CONFIG */
/* ========================================================================= */
#define UVH_LOCAL_INT0_CONFIG 0x61000UL
#define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0
#define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
#define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8
#define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL
#define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11
#define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
#define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12
#define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
#define UVH_LOCAL_INT0_CONFIG_P_SHFT 13
#define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL
#define UVH_LOCAL_INT0_CONFIG_T_SHFT 15
#define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL
#define UVH_LOCAL_INT0_CONFIG_M_SHFT 16
#define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL
#define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32
#define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
union uvh_local_int0_config_u {
unsigned long v;
struct uvh_local_int0_config_s {
unsigned long vector_ : 8; /* RW */
unsigned long dm : 3; /* RW */
unsigned long destmode : 1; /* RW */
unsigned long status : 1; /* RO */
unsigned long p : 1; /* RO */
unsigned long rsvd_14 : 1; /* */
unsigned long t : 1; /* RO */
unsigned long m : 1; /* RW */
unsigned long rsvd_17_31: 15; /* */
unsigned long apic_id : 32; /* RW */
} s;
};
/* ========================================================================= */
/* UVH_LOCAL_INT0_ENABLE */
/* ========================================================================= */
#define UVH_LOCAL_INT0_ENABLE 0x65000UL
#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0
#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL
#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1
#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL
#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2
#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL
#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3
#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL
#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4
#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL
#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5
#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL
#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6
#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL
#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7
#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL
#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8
#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL
#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9
#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL
#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10
#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL
#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11
#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL
#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12
#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL
#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13
#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL
#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14
#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL
#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15
#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL
#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16
#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL
#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17
#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL
#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18
#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL
#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19
#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL
#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20
#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL
#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21
#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL
#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22
#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38
#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL
#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39
#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL
#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40
#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL
#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41
#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL
#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42
#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL
#define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43
#define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL
#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44
#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
union uvh_local_int0_enable_u {
unsigned long v;
struct uvh_local_int0_enable_s {
unsigned long lb_hcerr : 1; /* RW */
unsigned long gr0_hcerr : 1; /* RW */
unsigned long gr1_hcerr : 1; /* RW */
unsigned long lh_hcerr : 1; /* RW */
unsigned long rh_hcerr : 1; /* RW */
unsigned long xn_hcerr : 1; /* RW */
unsigned long si_hcerr : 1; /* RW */
unsigned long lb_aoerr0 : 1; /* RW */
unsigned long gr0_aoerr0 : 1; /* RW */
unsigned long gr1_aoerr0 : 1; /* RW */
unsigned long lh_aoerr0 : 1; /* RW */
unsigned long rh_aoerr0 : 1; /* RW */
unsigned long xn_aoerr0 : 1; /* RW */
unsigned long si_aoerr0 : 1; /* RW */
unsigned long lb_aoerr1 : 1; /* RW */
unsigned long gr0_aoerr1 : 1; /* RW */
unsigned long gr1_aoerr1 : 1; /* RW */
unsigned long lh_aoerr1 : 1; /* RW */
unsigned long rh_aoerr1 : 1; /* RW */
unsigned long xn_aoerr1 : 1; /* RW */
unsigned long si_aoerr1 : 1; /* RW */
unsigned long rh_vpi_int : 1; /* RW */
unsigned long system_shutdown_int : 1; /* RW */
unsigned long lb_irq_int_0 : 1; /* RW */
unsigned long lb_irq_int_1 : 1; /* RW */
unsigned long lb_irq_int_2 : 1; /* RW */
unsigned long lb_irq_int_3 : 1; /* RW */
unsigned long lb_irq_int_4 : 1; /* RW */
unsigned long lb_irq_int_5 : 1; /* RW */
unsigned long lb_irq_int_6 : 1; /* RW */
unsigned long lb_irq_int_7 : 1; /* RW */
unsigned long lb_irq_int_8 : 1; /* RW */
unsigned long lb_irq_int_9 : 1; /* RW */
unsigned long lb_irq_int_10 : 1; /* RW */
unsigned long lb_irq_int_11 : 1; /* RW */
unsigned long lb_irq_int_12 : 1; /* RW */
unsigned long lb_irq_int_13 : 1; /* RW */
unsigned long lb_irq_int_14 : 1; /* RW */
unsigned long lb_irq_int_15 : 1; /* RW */
unsigned long l1_nmi_int : 1; /* RW */
unsigned long stop_clock : 1; /* RW */
unsigned long asic_to_l1 : 1; /* RW */
unsigned long l1_to_asic : 1; /* RW */
unsigned long ltc_int : 1; /* RW */
unsigned long la_seq_trigger : 1; /* RW */
unsigned long rsvd_45_63 : 19; /* */
} s;
};
/* ========================================================================= */ /* ========================================================================= */
/* UVH_NODE_ID */ /* UVH_NODE_ID */
/* ========================================================================= */ /* ========================================================================= */
@ -1111,26 +856,6 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
} s; } s;
}; };
/* ========================================================================= */
/* UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR */
/* ========================================================================= */
#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL
#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26
#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
union uvh_rh_gam_cfg_overlay_config_mmr_u {
unsigned long v;
struct uvh_rh_gam_cfg_overlay_config_mmr_s {
unsigned long rsvd_0_25: 26; /* */
unsigned long base : 20; /* RW */
unsigned long rsvd_46_62: 17; /* */
unsigned long enable : 1; /* RW */
} s;
};
/* ========================================================================= */ /* ========================================================================= */
/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
/* ========================================================================= */ /* ========================================================================= */
@ -1262,101 +987,6 @@ union uvh_rtc1_int_config_u {
} s; } s;
}; };
/* ========================================================================= */
/* UVH_RTC2_INT_CONFIG */
/* ========================================================================= */
#define UVH_RTC2_INT_CONFIG 0x61600UL
#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
#define UVH_RTC2_INT_CONFIG_P_SHFT 13
#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
#define UVH_RTC2_INT_CONFIG_T_SHFT 15
#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
#define UVH_RTC2_INT_CONFIG_M_SHFT 16
#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
union uvh_rtc2_int_config_u {
unsigned long v;
struct uvh_rtc2_int_config_s {
unsigned long vector_ : 8; /* RW */
unsigned long dm : 3; /* RW */
unsigned long destmode : 1; /* RW */
unsigned long status : 1; /* RO */
unsigned long p : 1; /* RO */
unsigned long rsvd_14 : 1; /* */
unsigned long t : 1; /* RO */
unsigned long m : 1; /* RW */
unsigned long rsvd_17_31: 15; /* */
unsigned long apic_id : 32; /* RW */
} s;
};
/* ========================================================================= */
/* UVH_RTC3_INT_CONFIG */
/* ========================================================================= */
#define UVH_RTC3_INT_CONFIG 0x61640UL
#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
#define UVH_RTC3_INT_CONFIG_P_SHFT 13
#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
#define UVH_RTC3_INT_CONFIG_T_SHFT 15
#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
#define UVH_RTC3_INT_CONFIG_M_SHFT 16
#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
union uvh_rtc3_int_config_u {
unsigned long v;
struct uvh_rtc3_int_config_s {
unsigned long vector_ : 8; /* RW */
unsigned long dm : 3; /* RW */
unsigned long destmode : 1; /* RW */
unsigned long status : 1; /* RO */
unsigned long p : 1; /* RO */
unsigned long rsvd_14 : 1; /* */
unsigned long t : 1; /* RO */
unsigned long m : 1; /* RW */
unsigned long rsvd_17_31: 15; /* */
unsigned long apic_id : 32; /* RW */
} s;
};
/* ========================================================================= */
/* UVH_RTC_INC_RATIO */
/* ========================================================================= */
#define UVH_RTC_INC_RATIO 0x350000UL
#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
union uvh_rtc_inc_ratio_u {
unsigned long v;
struct uvh_rtc_inc_ratio_s {
unsigned long fraction : 20; /* RW */
unsigned long ratio : 3; /* RW */
unsigned long rsvd_23_63: 41; /* */
} s;
};
/* ========================================================================= */ /* ========================================================================= */
/* UVH_SI_ADDR_MAP_CONFIG */ /* UVH_SI_ADDR_MAP_CONFIG */
/* ========================================================================= */ /* ========================================================================= */

3
arch/x86/kernel/apic/x2apic_uv_x.c
View file

@ -735,9 +735,6 @@ void __init uv_system_init(void)
uv_node_to_blade[nid] = blade; uv_node_to_blade[nid] = blade;
uv_cpu_to_blade[cpu] = blade; uv_cpu_to_blade[cpu] = blade;
max_pnode = max(pnode, max_pnode); max_pnode = max(pnode, max_pnode);
printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, lcpu %d, blade %d\n",
cpu, apicid, pnode, nid, lcpu, blade);
} }
/* Add blade/pnode info for nodes without cpus */ /* Add blade/pnode info for nodes without cpus */

1288
arch/x86/kernel/tlb_uv.c
View file

File diff suppressed because it is too large Load diff

12
arch/x86/kernel/uv_irq.c
View file

@ -44,7 +44,7 @@ static void uv_ack_apic(unsigned int irq)
ack_APIC_irq(); ack_APIC_irq();
} }
struct irq_chip uv_irq_chip = { static struct irq_chip uv_irq_chip = {
.name = "UV-CORE", .name = "UV-CORE",
.startup = uv_noop_ret, .startup = uv_noop_ret,
.shutdown = uv_noop, .shutdown = uv_noop,
@ -141,7 +141,7 @@ int uv_irq_2_mmr_info(int irq, unsigned long *offset, int *pnode)
*/ */
static int static int
arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
unsigned long mmr_offset, int restrict) unsigned long mmr_offset, int limit)
{ {
const struct cpumask *eligible_cpu = cpumask_of(cpu); const struct cpumask *eligible_cpu = cpumask_of(cpu);
struct irq_desc *desc = irq_to_desc(irq); struct irq_desc *desc = irq_to_desc(irq);
@ -160,7 +160,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
if (err != 0) if (err != 0)
return err; return err;
if (restrict == UV_AFFINITY_CPU) if (limit == UV_AFFINITY_CPU)
desc->status |= IRQ_NO_BALANCING; desc->status |= IRQ_NO_BALANCING;
else else
desc->status |= IRQ_MOVE_PCNTXT; desc->status |= IRQ_MOVE_PCNTXT;
@ -214,7 +214,7 @@ static int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
unsigned long mmr_value; unsigned long mmr_value;
struct uv_IO_APIC_route_entry *entry; struct uv_IO_APIC_route_entry *entry;
unsigned long mmr_offset; unsigned long mmr_offset;
unsigned mmr_pnode; int mmr_pnode;
if (set_desc_affinity(desc, mask, &dest)) if (set_desc_affinity(desc, mask, &dest))
return -1; return -1;
@ -248,7 +248,7 @@ static int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
* interrupt is raised. * interrupt is raised.
*/ */
int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
unsigned long mmr_offset, int restrict) unsigned long mmr_offset, int limit)
{ {
int irq, ret; int irq, ret;
@ -258,7 +258,7 @@ int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
return -EBUSY; return -EBUSY;
ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset, ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset,
restrict); limit);
if (ret == irq) if (ret == irq)
uv_set_irq_2_mmr_info(irq, mmr_offset, mmr_blade); uv_set_irq_2_mmr_info(irq, mmr_offset, mmr_blade);
else else