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ARM: dts: msm: add 2 lane support for msmcobalt ufs phy

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Qcom ufs controller v3.1.0 supports 2 lanes. Add necessary
clocks and lane config properties to support that.

Change-Id: I97b11dc21882f08327d7d056ce1bf1c34b3c3946
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This commit is contained in:
Venkat Gopalakrishnan 2016-08-18 16:58:30 -07:00
parent a58cf90d63
commit 54b8bf43e4
2 changed files with 50 additions and 1 deletions
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35
arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
View file

@ -570,3 +570,38 @@
};
};
};
&ufs1 {
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>,
<&clock_gcc clk_gcc_aggre1_ufs_axi_clk>,
<&clock_gcc clk_gcc_ufs_ahb_clk>,
<&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>,
<&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>,
<&clock_gcc clk_ln_bb_clk1>,
<&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,
<&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>,
<&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
lanes-per-direction = <2>;
};

16
arch/arm/boot/dts/qcom/msmcobalt.dtsi
View file

@ -1723,8 +1723,9 @@
<0 0>;
lanes-per-direction = <1>;
qcom,msm-bus,name = "ufs1";
qcom,msm-bus,num-cases = <12>;
qcom,msm-bus,num-cases = <22>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
<95 512 0 0>, <1 650 0 0>, /* No vote */
@ -1732,17 +1733,30 @@
<95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
<95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
<95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
<95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */
<95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */
<95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */
<95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */
<95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
<95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
<95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */
<95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */
<95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */
<95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */
<95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
<95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
<95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */
<95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */
<95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */
<95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */
<95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
"MAX";
/* PM QoS */