UPSTREAM: MIPS: Allow emulation for unaligned [LS]DXC1 instructions

If an address error exception occurs for a LDXC1 or SDXC1 instruction,
within the cop1x opcode space, allow it to be passed through to the FPU
emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to
be handled in a manner consistent with the more common LDC1 & SDC1
instructions.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit e70ac023f9515c70cf2b291a294f0f250df29847)
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Paul Burton 2016-04-21 12:25:38 +01:00 committed by Greg Kroah-Hartman
parent da8a6c79d7
commit 54c1aa3ea2

View file

@ -1191,6 +1191,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
case ldc1_op:
case swc1_op:
case sdc1_op:
case cop1x_op:
die_if_kernel("Unaligned FP access in kernel code", regs);
BUG_ON(!used_math());