From 54d865e4839fad4f725d35cf0646f0c44e65864d Mon Sep 17 00:00:00 2001
From: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Date: Fri, 23 Jun 2017 16:44:31 +0530
Subject: [PATCH] mdss: dp: set the proper parent for dp_vco_divided_clk_mux

The DP VCO divided mux clock has two parent dividers div_two
and div_four. The parent for this needs to be set based on the
link rate frequency as per the hardware programming guide and
not based on the auto PLL calculation logic. Add support to set
the correct parent for this.

Change-Id: Ia2d340a4e8790d90161c1f4a7c8273449fa3f53c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
---
 drivers/video/fbdev/msm/mdss_dp.c | 26 ++++++++++++++++++++++++++
 drivers/video/fbdev/msm/mdss_dp.h |  2 ++
 2 files changed, 28 insertions(+)

diff --git a/drivers/video/fbdev/msm/mdss_dp.c b/drivers/video/fbdev/msm/mdss_dp.c
index bc325a91a9bf..6b003239ed34 100644
--- a/drivers/video/fbdev/msm/mdss_dp.c
+++ b/drivers/video/fbdev/msm/mdss_dp.c
@@ -422,6 +422,22 @@ static int mdss_dp_clk_init(struct mdss_dp_drv_pdata *dp_drv,
 				__func__);
 			dp_drv->pixel_parent = NULL;
 		}
+
+		dp_drv->pixel_clk_two_div = devm_clk_get(dev,
+			"pixel_clk_two_div");
+		if (IS_ERR(dp_drv->pixel_clk_two_div)) {
+			pr_debug("%s: Unable to get DP pixel two div clk\n",
+				__func__);
+			dp_drv->pixel_clk_two_div = NULL;
+		}
+
+		dp_drv->pixel_clk_four_div = devm_clk_get(dev,
+			"pixel_clk_four_div");
+		if (IS_ERR(dp_drv->pixel_clk_four_div)) {
+			pr_debug("%s: Unable to get DP pixel four div clk\n",
+				__func__);
+			dp_drv->pixel_clk_four_div = NULL;
+		}
 	} else {
 		if (dp_drv->pixel_parent)
 			devm_clk_put(dev, dp_drv->pixel_parent);
@@ -1418,6 +1434,16 @@ static int mdss_dp_enable_mainlink_clocks(struct mdss_dp_drv_pdata *dp)
 		return ret;
 	}
 
+	if (dp->pixel_parent && dp->pixel_clk_two_div &&
+		dp->pixel_clk_four_div) {
+		if (dp->link_rate == DP_LINK_RATE_540)
+			clk_set_parent(dp->pixel_parent,
+				dp->pixel_clk_four_div);
+		else
+			clk_set_parent(dp->pixel_parent,
+				dp->pixel_clk_two_div);
+	}
+
 	mdss_dp_set_clock_rate(dp, "ctrl_link_clk",
 		(dp->link_rate * DP_LINK_RATE_MULTIPLIER) / DP_KHZ_TO_HZ);
 
diff --git a/drivers/video/fbdev/msm/mdss_dp.h b/drivers/video/fbdev/msm/mdss_dp.h
index 983f5e34a515..f3f9ca277762 100644
--- a/drivers/video/fbdev/msm/mdss_dp.h
+++ b/drivers/video/fbdev/msm/mdss_dp.h
@@ -614,6 +614,8 @@ struct mdss_dp_drv_pdata {
 	/* DP Pixel clock RCG and PLL parent */
 	struct clk *pixel_clk_rcg;
 	struct clk *pixel_parent;
+	struct clk *pixel_clk_two_div;
+	struct clk *pixel_clk_four_div;
 
 	/* regulators */
 	struct dss_module_power power_data[DP_MAX_PM];