ARM: dts: msm: increase PCIe PHY wakeup delay from L1ss for msm8998

If PCIe controller requests exit from L1ss shortly after it brings
rxelecidle_disable high, then it's possible that the PHY pipe clock
will turn back on for a short period of time and then go back off
asychronously. Increase PCIe PHY PLL wakeup delay to avoid this.

Change-Id: I1cace039131879969112e1690d07a8d367c06c6b
Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong 2017-05-04 11:47:14 -07:00 committed by Rama Krishna Phani A
parent a49bb61510
commit 553433ff26
2 changed files with 2 additions and 2 deletions

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0x9dc 0x01 0x00 0x9dc 0x20 0x00
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0x9ac 0x00 0x00 0x9ac 0x00 0x00
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0x9dc 0x01 0x00 0x9dc 0x20 0x00
0x9a8 0x00 0x00 0x9a8 0x00 0x00
0x8a4 0x01 0x00 0x8a4 0x01 0x00
0x8a8 0x73 0x00 0x8a8 0x73 0x00