evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

clk: mdss: Remove pll support for all targets except msm8996

Browse source 
As part of 3.18 upgrade, remove support pll support for all
other targets except msm8996.

Change-Id: Idc778ccba25ce22ad7e418c45f2bd8d21ccb95e8
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This commit is contained in:
Veera Sundaram Sankaran 2015-04-14 18:21:49 -07:00 • committed by David Keitel
parent 62a6355138
commit 56c32840d4
13 changed files with 9 additions and 5649 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
drivers/clk/msm/mdss/Makefile
View file

@ -1,12 +1,5 @@
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-util.o mdss-dsi-20nm-pll-util.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28lpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-20nm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o

1011
drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c
View file

File diff suppressed because it is too large Load diff

608
drivers/clk/msm/mdss/mdss-dsi-pll-20nm.c
View file

@ -1,608 +0,0 @@
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clk/msm-clk-provider.h>
#include <linux/clk/msm-clk.h>
#include <linux/workqueue.h>
#include <linux/clk/msm-clock-generic.h>
#include <dt-bindings/clock/msm-clocks-8994.h>
#include "mdss-pll.h"
#include "mdss-dsi-pll.h"
#define VCO_DELAY_USEC 1
static struct clk_ops bypass_lp_div_mux_clk_ops;
static struct clk_ops pixel_clk_src_ops;
static struct clk_ops byte_clk_src_ops;
static struct clk_ops ndiv_clk_ops;
static struct clk_ops shadow_pixel_clk_src_ops;
static struct clk_ops shadow_byte_clk_src_ops;
static struct clk_ops clk_ops_gen_mux_dsi;
static int vco_set_rate_20nm(struct clk *c, unsigned long rate)
{
int rc;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
pr_debug("Cancel pending pll off work\n");
cancel_work_sync(&dsi_pll_res->pll_off);
rc = pll_20nm_vco_set_rate(vco, rate);
mdss_pll_resource_enable(dsi_pll_res, false);
return rc;
}
static int pll1_vco_set_rate_20nm(struct clk *c, unsigned long rate)
{
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *pll_res = vco->priv;
mdss_pll_resource_enable(pll_res, true);
__dsi_pll_disable(pll_res->pll_base);
mdss_pll_resource_enable(pll_res, false);
pr_debug("Configuring PLL1 registers.\n");
return 0;
}
static int shadow_vco_set_rate_20nm(struct clk *c, unsigned long rate)
{
int rc;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
if (!dsi_pll_res->resource_enable) {
pr_err("PLL resources disabled. Dynamic fps invalid\n");
return -EINVAL;
}
rc = shadow_pll_20nm_vco_set_rate(vco, rate);
return rc;
}
/* Op structures */
static struct clk_ops pll1_clk_ops_dsi_vco = {
.set_rate = pll1_vco_set_rate_20nm,
};
static struct clk_ops clk_ops_dsi_vco = {
.set_rate = vco_set_rate_20nm,
.round_rate = pll_20nm_vco_round_rate,
.handoff = pll_20nm_vco_handoff,
.prepare = pll_20nm_vco_prepare,
.unprepare = pll_20nm_vco_unprepare,
};
static struct clk_div_ops fixed_hr_oclk2_div_ops = {
.set_div = fixed_hr_oclk2_set_div,
.get_div = fixed_hr_oclk2_get_div,
};
static struct clk_div_ops ndiv_ops = {
.set_div = ndiv_set_div,
.get_div = ndiv_get_div,
};
static struct clk_div_ops hr_oclk3_div_ops = {
.set_div = hr_oclk3_set_div,
.get_div = hr_oclk3_get_div,
};
static struct clk_mux_ops bypass_lp_div_mux_ops = {
.set_mux_sel = set_bypass_lp_div_mux_sel,
.get_mux_sel = get_bypass_lp_div_mux_sel,
};
static struct clk_ops shadow_clk_ops_dsi_vco = {
.set_rate = shadow_vco_set_rate_20nm,
.round_rate = pll_20nm_vco_round_rate,
.handoff = pll_20nm_vco_handoff,
};
static struct clk_div_ops shadow_fixed_hr_oclk2_div_ops = {
.set_div = shadow_fixed_hr_oclk2_set_div,
.get_div = fixed_hr_oclk2_get_div,
};
static struct clk_div_ops shadow_ndiv_ops = {
.set_div = shadow_ndiv_set_div,
.get_div = ndiv_get_div,
};
static struct clk_div_ops shadow_hr_oclk3_div_ops = {
.set_div = shadow_hr_oclk3_set_div,
.get_div = hr_oclk3_get_div,
};
static struct clk_mux_ops shadow_bypass_lp_div_mux_ops = {
.set_mux_sel = set_shadow_bypass_lp_div_mux_sel,
.get_mux_sel = get_bypass_lp_div_mux_sel,
};
static struct clk_mux_ops mdss_byte_mux_ops = {
.set_mux_sel = set_mdss_byte_mux_sel,
.get_mux_sel = get_mdss_byte_mux_sel,
};
static struct clk_mux_ops mdss_pixel_mux_ops = {
.set_mux_sel = set_mdss_pixel_mux_sel,
.get_mux_sel = get_mdss_pixel_mux_sel,
};
static struct dsi_pll_vco_clk mdss_dsi1_vco_clk_src = {
.c = {
.dbg_name = "mdss_dsi1_vco_clk_src",
.ops = &pll1_clk_ops_dsi_vco,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(mdss_dsi1_vco_clk_src.c),
},
};
static struct dsi_pll_vco_clk dsi_vco_clk_8994 = {
.ref_clk_rate = 19200000,
.min_rate = 300000000,
.max_rate = 1500000000,
.pll_en_seq_cnt = 1,
.pll_enable_seqs[0] = pll_20nm_vco_enable_seq,
.c = {
.dbg_name = "dsi_vco_clk_8994",
.ops = &clk_ops_dsi_vco,
CLK_INIT(dsi_vco_clk_8994.c),
},
};
static struct dsi_pll_vco_clk shadow_dsi_vco_clk_8994 = {
.ref_clk_rate = 19200000,
.min_rate = 300000000,
.max_rate = 1500000000,
.c = {
.dbg_name = "shadow_dsi_vco_clk_8994",
.ops = &shadow_clk_ops_dsi_vco,
CLK_INIT(shadow_dsi_vco_clk_8994.c),
},
};
static struct div_clk ndiv_clk_8994 = {
.data = {
.max_div = 15,
.min_div = 1,
},
.ops = &ndiv_ops,
.c = {
.parent = &dsi_vco_clk_8994.c,
.dbg_name = "ndiv_clk_8994",
.ops = &ndiv_clk_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(ndiv_clk_8994.c),
},
};
static struct div_clk shadow_ndiv_clk_8994 = {
.data = {
.max_div = 15,
.min_div = 1,
},
.ops = &shadow_ndiv_ops,
.c = {
.parent = &shadow_dsi_vco_clk_8994.c,
.dbg_name = "shadow_ndiv_clk_8994",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(shadow_ndiv_clk_8994.c),
},
};
static struct div_clk indirect_path_div2_clk_8994 = {
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &ndiv_clk_8994.c,
.dbg_name = "indirect_path_div2_clk_8994",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(indirect_path_div2_clk_8994.c),
},
};
static struct div_clk shadow_indirect_path_div2_clk_8994 = {
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &shadow_ndiv_clk_8994.c,
.dbg_name = "shadow_indirect_path_div2_clk_8994",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(shadow_indirect_path_div2_clk_8994.c),
},
};
static struct div_clk hr_oclk3_div_clk_8994 = {
.data = {
.max_div = 255,
.min_div = 1,
},
.ops = &hr_oclk3_div_ops,
.c = {
.parent = &dsi_vco_clk_8994.c,
.dbg_name = "hr_oclk3_div_clk_8994",
.ops = &pixel_clk_src_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(hr_oclk3_div_clk_8994.c),
},
};
static struct div_clk shadow_hr_oclk3_div_clk_8994 = {
.data = {
.max_div = 255,
.min_div = 1,
},
.ops = &shadow_hr_oclk3_div_ops,
.c = {
.parent = &shadow_dsi_vco_clk_8994.c,
.dbg_name = "shadow_hr_oclk3_div_clk_8994",
.ops = &shadow_pixel_clk_src_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(shadow_hr_oclk3_div_clk_8994.c),
},
};
static struct div_clk pixel_clk_src = {
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &hr_oclk3_div_clk_8994.c,
.dbg_name = "pixel_clk_src",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(pixel_clk_src.c),
},
};
static struct div_clk shadow_pixel_clk_src = {
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &shadow_hr_oclk3_div_clk_8994.c,
.dbg_name = "shadow_pixel_clk_src",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(shadow_pixel_clk_src.c),
},
};
static struct mux_clk bypass_lp_div_mux_8994 = {
.num_parents = 2,
.parents = (struct clk_src[]){
{&dsi_vco_clk_8994.c, 0},
{&indirect_path_div2_clk_8994.c, 1},
},
.ops = &bypass_lp_div_mux_ops,
.c = {
.parent = &dsi_vco_clk_8994.c,
.dbg_name = "bypass_lp_div_mux_8994",
.ops = &bypass_lp_div_mux_clk_ops,
CLK_INIT(bypass_lp_div_mux_8994.c),
},
};
static struct mux_clk shadow_bypass_lp_div_mux_8994 = {
.num_parents = 2,
.parents = (struct clk_src[]){
{&shadow_dsi_vco_clk_8994.c, 0},
{&shadow_indirect_path_div2_clk_8994.c, 1},
},
.ops = &shadow_bypass_lp_div_mux_ops,
.c = {
.parent = &shadow_dsi_vco_clk_8994.c,
.dbg_name = "shadow_bypass_lp_div_mux_8994",
.ops = &clk_ops_gen_mux,
CLK_INIT(shadow_bypass_lp_div_mux_8994.c),
},
};
static struct div_clk fixed_hr_oclk2_div_clk_8994 = {
.ops = &fixed_hr_oclk2_div_ops,
.data = {
.min_div = 4,
.max_div = 4,
},
.c = {
.parent = &bypass_lp_div_mux_8994.c,
.dbg_name = "fixed_hr_oclk2_div_clk_8994",
.ops = &byte_clk_src_ops,
CLK_INIT(fixed_hr_oclk2_div_clk_8994.c),
},
};
static struct div_clk shadow_fixed_hr_oclk2_div_clk_8994 = {
.ops = &shadow_fixed_hr_oclk2_div_ops,
.data = {
.min_div = 4,
.max_div = 4,
},
.c = {
.parent = &shadow_bypass_lp_div_mux_8994.c,
.dbg_name = "shadow_fixed_hr_oclk2_div_clk_8994",
.ops = &shadow_byte_clk_src_ops,
CLK_INIT(shadow_fixed_hr_oclk2_div_clk_8994.c),
},
};
static struct div_clk byte_clk_src = {
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &fixed_hr_oclk2_div_clk_8994.c,
.dbg_name = "byte_clk_src",
.ops = &clk_ops_div,
CLK_INIT(byte_clk_src.c),
},
};
static struct div_clk shadow_byte_clk_src = {
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &shadow_fixed_hr_oclk2_div_clk_8994.c,
.dbg_name = "shadow_byte_clk_src",
.ops = &clk_ops_div,
CLK_INIT(shadow_byte_clk_src.c),
},
};
static struct mux_clk mdss_pixel_clk_mux = {
.num_parents = 2,
.parents = (struct clk_src[]) {
{&pixel_clk_src.c, 0},
{&shadow_pixel_clk_src.c, 1},
},
.ops = &mdss_pixel_mux_ops,
.c = {
.parent = &pixel_clk_src.c,
.dbg_name = "mdss_pixel_clk_mux",
.ops = &clk_ops_gen_mux,
CLK_INIT(mdss_pixel_clk_mux.c),
}
};
static struct mux_clk mdss_byte_clk_mux = {
.num_parents = 2,
.parents = (struct clk_src[]) {
{&byte_clk_src.c, 0},
{&shadow_byte_clk_src.c, 1},
},
.ops = &mdss_byte_mux_ops,
.c = {
.parent = &byte_clk_src.c,
.dbg_name = "mdss_byte_clk_mux",
.ops = &clk_ops_gen_mux_dsi,
CLK_INIT(mdss_byte_clk_mux.c),
}
};
static struct clk_lookup mdss_dsi_pll_1_cc_8994[] = {
CLK_LIST(mdss_dsi1_vco_clk_src),
};
static struct clk_lookup mdss_dsi_pllcc_8994[] = {
CLK_LIST(mdss_pixel_clk_mux),
CLK_LIST(mdss_byte_clk_mux),
CLK_LIST(pixel_clk_src),
CLK_LIST(byte_clk_src),
CLK_LIST(fixed_hr_oclk2_div_clk_8994),
CLK_LIST(bypass_lp_div_mux_8994),
CLK_LIST(hr_oclk3_div_clk_8994),
CLK_LIST(indirect_path_div2_clk_8994),
CLK_LIST(ndiv_clk_8994),
CLK_LIST(dsi_vco_clk_8994),
CLK_LIST(shadow_pixel_clk_src),
CLK_LIST(shadow_byte_clk_src),
CLK_LIST(shadow_fixed_hr_oclk2_div_clk_8994),
CLK_LIST(shadow_bypass_lp_div_mux_8994),
CLK_LIST(shadow_hr_oclk3_div_clk_8994),
CLK_LIST(shadow_indirect_path_div2_clk_8994),
CLK_LIST(shadow_ndiv_clk_8994),
CLK_LIST(shadow_dsi_vco_clk_8994),
};
static void dsi_pll_off_work(struct work_struct *work)
{
struct mdss_pll_resources *pll_res;
if (!work) {
pr_err("pll_resource is invalid\n");
return;
}
pr_debug("Starting PLL off Worker%s\n", __func__);
pll_res = container_of(work, struct
mdss_pll_resources, pll_off);
mdss_pll_resource_enable(pll_res, true);
__dsi_pll_disable(pll_res->pll_base);
if (pll_res->pll_1_base)
__dsi_pll_disable(pll_res->pll_1_base);
mdss_pll_resource_enable(pll_res, false);
}
static int dsi_pll_regulator_notifier_call(struct notifier_block *self,
unsigned long event, void *data)
{
struct mdss_pll_resources *pll_res;
if (!self) {
pr_err("pll_resource is invalid\n");
goto error;
}
pll_res = container_of(self, struct
mdss_pll_resources, gdsc_cb);
if (event & REGULATOR_EVENT_ENABLE) {
pr_debug("Regulator ON event. Scheduling pll off worker\n");
schedule_work(&pll_res->pll_off);
}
if (event & REGULATOR_EVENT_DISABLE)
pr_debug("Regulator OFF event.\n");
error:
return NOTIFY_OK;
}
int dsi_pll_clock_register_20nm(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc;
struct dss_vreg *pll_reg;
if (!pdev || !pdev->dev.of_node) {
pr_err("Invalid input parameters\n");
return -EINVAL;
}
if (!pll_res || !pll_res->pll_base) {
pr_err("Invalid PLL resources\n");
return -EPROBE_DEFER;
}
/*
* Set client data to mux, div and vco clocks.
* This needs to be done only for PLL0 since, that is the one in
* use.
**/
if (!pll_res->index) {
byte_clk_src.priv = pll_res;
pixel_clk_src.priv = pll_res;
bypass_lp_div_mux_8994.priv = pll_res;
indirect_path_div2_clk_8994.priv = pll_res;
ndiv_clk_8994.priv = pll_res;
fixed_hr_oclk2_div_clk_8994.priv = pll_res;
hr_oclk3_div_clk_8994.priv = pll_res;
dsi_vco_clk_8994.priv = pll_res;
shadow_byte_clk_src.priv = pll_res;
shadow_pixel_clk_src.priv = pll_res;
shadow_bypass_lp_div_mux_8994.priv = pll_res;
shadow_indirect_path_div2_clk_8994.priv = pll_res;
shadow_ndiv_clk_8994.priv = pll_res;
shadow_fixed_hr_oclk2_div_clk_8994.priv = pll_res;
shadow_hr_oclk3_div_clk_8994.priv = pll_res;
shadow_dsi_vco_clk_8994.priv = pll_res;
pll_res->vco_delay = VCO_DELAY_USEC;
/* Set clock source operations */
pixel_clk_src_ops = clk_ops_slave_div;
pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
ndiv_clk_ops = clk_ops_div;
ndiv_clk_ops.prepare = dsi_pll_div_prepare;
byte_clk_src_ops = clk_ops_div;
byte_clk_src_ops.prepare = dsi_pll_div_prepare;
bypass_lp_div_mux_clk_ops = clk_ops_gen_mux;
bypass_lp_div_mux_clk_ops.prepare = dsi_pll_mux_prepare;
clk_ops_gen_mux_dsi = clk_ops_gen_mux;
clk_ops_gen_mux_dsi.round_rate = parent_round_rate;
clk_ops_gen_mux_dsi.set_rate = parent_set_rate;
shadow_pixel_clk_src_ops = clk_ops_slave_div;
shadow_pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
shadow_byte_clk_src_ops = clk_ops_div;
shadow_byte_clk_src_ops.prepare = dsi_pll_div_prepare;
} else {
mdss_dsi1_vco_clk_src.priv = pll_res;
}
if ((pll_res->target_id == MDSS_PLL_TARGET_8994) ||
(pll_res->target_id == MDSS_PLL_TARGET_8992)) {
if (pll_res->index) {
rc = of_msm_clock_register(pdev->dev.of_node,
mdss_dsi_pll_1_cc_8994,
ARRAY_SIZE(mdss_dsi_pll_1_cc_8994));
if (rc) {
pr_err("Clock register failed\n");
rc = -EPROBE_DEFER;
}
} else {
rc = of_msm_clock_register(pdev->dev.of_node,
mdss_dsi_pllcc_8994,
ARRAY_SIZE(mdss_dsi_pllcc_8994));
if (rc) {
pr_err("Clock register failed\n");
rc = -EPROBE_DEFER;
}
pll_res->gdsc_cb.notifier_call =
dsi_pll_regulator_notifier_call;
INIT_WORK(&pll_res->pll_off, dsi_pll_off_work);
pll_reg = mdss_pll_get_mp_by_reg_name(pll_res, "gdsc");
if (pll_reg) {
pr_debug("Registering for gdsc regulator events\n");
if (regulator_register_notifier(pll_reg->vreg,
&(pll_res->gdsc_cb)))
pr_err("Regulator notification registration failed!\n");
}
}
} else {
pr_err("Invalid target ID\n");
rc = -EINVAL;
}
if (!rc)
pr_info("Registered DSI PLL clocks successfully\n");
return rc;
}

335
drivers/clk/msm/mdss/mdss-dsi-pll-28hpm.c
View file

@ -1,335 +0,0 @@
/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clk/msm-clk-provider.h>
#include <linux/clk/msm-clk.h>
#include <linux/clk/msm-clock-generic.h>
#include <dt-bindings/clock/msm-clocks-8974.h>
#include "mdss-pll.h"
#include "mdss-dsi-pll.h"
#define VCO_DELAY_USEC 1
static struct clk_div_ops fixed_2div_ops;
static struct clk_ops byte_mux_clk_ops;
static struct clk_ops pixel_clk_src_ops;
static struct clk_ops byte_clk_src_ops;
static struct clk_ops analog_postdiv_clk_ops;
static struct lpfr_cfg lpfr_lut_struct[] = {
{479500000, 8},
{480000000, 11},
{575500000, 8},
{576000000, 12},
{610500000, 8},
{659500000, 9},
{671500000, 10},
{672000000, 14},
{708500000, 10},
{750000000, 11},
};
static void dsi_pll_software_reset(struct mdss_pll_resources *dsi_pll_res)
{
/*
* Add HW recommended delays after toggling the software
* reset bit off and back on.
*/
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
udelay(1);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
udelay(1);
}
static int vco_set_rate_hpm(struct clk *c, unsigned long rate)
{
int rc;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
rc = vco_set_rate(vco, rate);
mdss_pll_resource_enable(dsi_pll_res, false);
return rc;
}
static int dsi_pll_enable_seq_8974(struct mdss_pll_resources *dsi_pll_res)
{
int i, rc = 0;
int pll_locked;
dsi_pll_software_reset(dsi_pll_res);
/*
* PLL power up sequence.
* Add necessary delays recommeded by hardware.
*/
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
udelay(1);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
udelay(200);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
udelay(500);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
udelay(500);
for (i = 0; i < 2; i++) {
udelay(100);
/* DSI Uniphy lock detect setting */
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0c);
udelay(100);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
pll_locked = dsi_pll_lock_status(dsi_pll_res);
if (pll_locked)
break;
dsi_pll_software_reset(dsi_pll_res);
/*
* PLL power up sequence.
* Add necessary delays recommeded by hardware.
*/
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x1);
udelay(1);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
udelay(200);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
udelay(250);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
udelay(200);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
udelay(500);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0xf);
udelay(500);
}
if (!pll_locked) {
pr_err("DSI PLL lock failed\n");
rc = -EINVAL;
} else {
pr_debug("DSI PLL Lock success\n");
}
return rc;
}
/* Op structures */
static struct clk_ops clk_ops_dsi_vco = {
.set_rate = vco_set_rate_hpm,
.round_rate = vco_round_rate,
.handoff = vco_handoff,
.prepare = vco_prepare,
.unprepare = vco_unprepare,
};
static struct clk_div_ops fixed_4div_ops = {
.set_div = fixed_4div_set_div,
.get_div = fixed_4div_get_div,
};
static struct clk_div_ops analog_postdiv_ops = {
.set_div = analog_set_div,
.get_div = analog_get_div,
};
static struct clk_div_ops digital_postdiv_ops = {
.set_div = digital_set_div,
.get_div = digital_get_div,
};
static struct clk_mux_ops byte_mux_ops = {
.set_mux_sel = set_byte_mux_sel,
.get_mux_sel = get_byte_mux_sel,
};
static struct dsi_pll_vco_clk dsi_vco_clk_8974 = {
.ref_clk_rate = 19200000,
.min_rate = 350000000,
.max_rate = 750000000,
.pll_en_seq_cnt = 3,
.pll_enable_seqs[0] = dsi_pll_enable_seq_8974,
.pll_enable_seqs[1] = dsi_pll_enable_seq_8974,
.pll_enable_seqs[2] = dsi_pll_enable_seq_8974,
.lpfr_lut_size = 10,
.lpfr_lut = lpfr_lut_struct,
.c = {
.dbg_name = "dsi_vco_clk_8974",
.ops = &clk_ops_dsi_vco,
CLK_INIT(dsi_vco_clk_8974.c),
},
};
static struct div_clk analog_postdiv_clk_8974 = {
.data = {
.max_div = 255,
.min_div = 1,
},
.ops = &analog_postdiv_ops,
.c = {
.parent = &dsi_vco_clk_8974.c,
.dbg_name = "analog_postdiv_clk",
.ops = &analog_postdiv_clk_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(analog_postdiv_clk_8974.c),
},
};
static struct div_clk indirect_path_div2_clk_8974 = {
.ops = &fixed_2div_ops,
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &analog_postdiv_clk_8974.c,
.dbg_name = "indirect_path_div2_clk",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(indirect_path_div2_clk_8974.c),
},
};
static struct div_clk pixel_clk_src_8974 = {
.data = {
.max_div = 255,
.min_div = 1,
},
.ops = &digital_postdiv_ops,
.c = {
.parent = &dsi_vco_clk_8974.c,
.dbg_name = "pixel_clk_src_8974",
.ops = &pixel_clk_src_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(pixel_clk_src_8974.c),
},
};
static struct mux_clk byte_mux_8974 = {
.num_parents = 2,
.parents = (struct clk_src[]){
{&dsi_vco_clk_8974.c, 0},
{&indirect_path_div2_clk_8974.c, 1},
},
.ops = &byte_mux_ops,
.c = {
.parent = &dsi_vco_clk_8974.c,
.dbg_name = "byte_mux_8974",
.ops = &byte_mux_clk_ops,
CLK_INIT(byte_mux_8974.c),
},
};
static struct div_clk byte_clk_src_8974 = {
.ops = &fixed_4div_ops,
.data = {
.min_div = 4,
.max_div = 4,
},
.c = {
.parent = &byte_mux_8974.c,
.dbg_name = "byte_clk_src_8974",
.ops = &byte_clk_src_ops,
CLK_INIT(byte_clk_src_8974.c),
},
};
static struct clk_lookup mdss_dsi_pllcc_8974[] = {
CLK_LOOKUP_OF("pixel_src", pixel_clk_src_8974,
"fd8c0000.qcom,mmsscc-mdss"),
CLK_LOOKUP_OF("byte_src", byte_clk_src_8974,
"fd8c0000.qcom,mmsscc-mdss"),
};
int dsi_pll_clock_register_hpm(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc;
if (!pdev || !pdev->dev.of_node) {
pr_err("Invalid input parameters\n");
return -EINVAL;
}
if (!pll_res || !pll_res->pll_base) {
pr_err("Invalid PLL resources\n");
return -EPROBE_DEFER;
}
/* Set client data to mux, div and vco clocks */
byte_clk_src_8974.priv = pll_res;
pixel_clk_src_8974.priv = pll_res;
byte_mux_8974.priv = pll_res;
indirect_path_div2_clk_8974.priv = pll_res;
analog_postdiv_clk_8974.priv = pll_res;
dsi_vco_clk_8974.priv = pll_res;
pll_res->vco_delay = VCO_DELAY_USEC;
/* Set clock source operations */
pixel_clk_src_ops = clk_ops_slave_div;
pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
analog_postdiv_clk_ops = clk_ops_div;
analog_postdiv_clk_ops.prepare = dsi_pll_div_prepare;
byte_clk_src_ops = clk_ops_div;
byte_clk_src_ops.prepare = dsi_pll_div_prepare;
byte_mux_clk_ops = clk_ops_gen_mux;
byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;
if (pll_res->target_id == MDSS_PLL_TARGET_8974) {
rc = of_msm_clock_register(pdev->dev.of_node,
mdss_dsi_pllcc_8974, ARRAY_SIZE(mdss_dsi_pllcc_8974));
if (rc) {
pr_err("Clock register failed\n");
rc = -EPROBE_DEFER;
}
} else {
pr_err("Invalid target ID\n");
rc = -EINVAL;
}
if (!rc)
pr_info("Registered DSI PLL clocks successfully\n");
return rc;
}

306
drivers/clk/msm/mdss/mdss-dsi-pll-28lpm.c
View file

@ -1,306 +0,0 @@
/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clk/msm-clk.h>
#include <linux/clk/msm-clock-generic.h>
#include <linux/clk/msm-clk-provider.h>
#include <dt-bindings/clock/msm-clocks-8916.h>
#include "mdss-pll.h"
#include "mdss-dsi-pll.h"
#define VCO_DELAY_USEC 1000
static struct clk_div_ops fixed_2div_ops;
static struct clk_ops byte_mux_clk_ops;
static struct clk_ops pixel_clk_src_ops;
static struct clk_ops byte_clk_src_ops;
static struct clk_ops analog_postdiv_clk_ops;
static struct lpfr_cfg lpfr_lut_struct[] = {
{479500000, 8},
{480000000, 11},
{575500000, 8},
{576000000, 12},
{610500000, 8},
{659500000, 9},
{671500000, 10},
{672000000, 14},
{708500000, 10},
{750000000, 11},
};
static int vco_set_rate_lpm(struct clk *c, unsigned long rate)
{
int rc;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
/*
* DSI PLL software reset. Add HW recommended delays after toggling
* the software reset bit off and back on.
*/
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
udelay(1000);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
udelay(1000);
rc = vco_set_rate(vco, rate);
mdss_pll_resource_enable(dsi_pll_res, false);
return rc;
}
static int dsi_pll_enable_seq_8916(struct mdss_pll_resources *dsi_pll_res)
{
int pll_locked = 0;
/*
* DSI PLL software reset. Add HW recommended delays after toggling
* the software reset bit off and back on.
*/
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
ndelay(500);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
/*
* PLL power up sequence.
* Add necessary delays recommended by hardware.
*/
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x34);
ndelay(500);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
ndelay(500);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
ndelay(500);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
ndelay(500);
/* DSI PLL toggle lock detect setting */
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x04);
ndelay(500);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05);
udelay(512);
pll_locked = dsi_pll_lock_status(dsi_pll_res);
if (pll_locked)
pr_debug("PLL Locked\n");
else
pr_err("PLL failed to lock\n");
return pll_locked ? 0 : -EINVAL;
}
/* Op structures */
static struct clk_ops clk_ops_dsi_vco = {
.set_rate = vco_set_rate_lpm,
.round_rate = vco_round_rate,
.handoff = vco_handoff,
.prepare = vco_prepare,
.unprepare = vco_unprepare,
};
static struct clk_div_ops fixed_4div_ops = {
.set_div = fixed_4div_set_div,
.get_div = fixed_4div_get_div,
};
static struct clk_div_ops analog_postdiv_ops = {
.set_div = analog_set_div,
.get_div = analog_get_div,
};
static struct clk_div_ops digital_postdiv_ops = {
.set_div = digital_set_div,
.get_div = digital_get_div,
};
static struct clk_mux_ops byte_mux_ops = {
.set_mux_sel = set_byte_mux_sel,
.get_mux_sel = get_byte_mux_sel,
};
static struct dsi_pll_vco_clk dsi_vco_clk_8916 = {
.ref_clk_rate = 19200000,
.min_rate = 350000000,
.max_rate = 750000000,
.pll_en_seq_cnt = 1,
.pll_enable_seqs[0] = dsi_pll_enable_seq_8916,
.lpfr_lut_size = 10,
.lpfr_lut = lpfr_lut_struct,
.c = {
.dbg_name = "dsi_vco_clk_8916",
.ops = &clk_ops_dsi_vco,
CLK_INIT(dsi_vco_clk_8916.c),
},
};
static struct div_clk analog_postdiv_clk_8916 = {
.data = {
.max_div = 255,
.min_div = 1,
},
.ops = &analog_postdiv_ops,
.c = {
.parent = &dsi_vco_clk_8916.c,
.dbg_name = "analog_postdiv_clk",
.ops = &analog_postdiv_clk_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(analog_postdiv_clk_8916.c),
},
};
static struct div_clk indirect_path_div2_clk_8916 = {
.ops = &fixed_2div_ops,
.data = {
.div = 2,
.min_div = 2,
.max_div = 2,
},
.c = {
.parent = &analog_postdiv_clk_8916.c,
.dbg_name = "indirect_path_div2_clk",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(indirect_path_div2_clk_8916.c),
},
};
static struct div_clk pixel_clk_src = {
.data = {
.max_div = 255,
.min_div = 1,
},
.ops = &digital_postdiv_ops,
.c = {
.parent = &dsi_vco_clk_8916.c,
.dbg_name = "pixel_clk_src_8916",
.ops = &pixel_clk_src_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(pixel_clk_src.c),
},
};
static struct mux_clk byte_mux_8916 = {
.num_parents = 2,
.parents = (struct clk_src[]){
{&dsi_vco_clk_8916.c, 0},
{&indirect_path_div2_clk_8916.c, 1},
},
.ops = &byte_mux_ops,
.c = {
.parent = &dsi_vco_clk_8916.c,
.dbg_name = "byte_mux_8916",
.ops = &byte_mux_clk_ops,
CLK_INIT(byte_mux_8916.c),
},
};
static struct div_clk byte_clk_src = {
.ops = &fixed_4div_ops,
.data = {
.min_div = 4,
.max_div = 4,
},
.c = {
.parent = &byte_mux_8916.c,
.dbg_name = "byte_clk_src_8916",
.ops = &byte_clk_src_ops,
CLK_INIT(byte_clk_src.c),
},
};
static struct clk_lookup mdss_dsi_pllcc_8916[] = {
CLK_LIST(pixel_clk_src),
CLK_LIST(byte_clk_src),
};
int dsi_pll_clock_register_lpm(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc;
if (!pdev || !pdev->dev.of_node) {
pr_err("Invalid input parameters\n");
return -EINVAL;
}
if (!pll_res || !pll_res->pll_base) {
pr_err("Invalid PLL resources\n");
return -EPROBE_DEFER;
}
/* Set client data to mux, div and vco clocks */
byte_clk_src.priv = pll_res;
pixel_clk_src.priv = pll_res;
byte_mux_8916.priv = pll_res;
indirect_path_div2_clk_8916.priv = pll_res;
analog_postdiv_clk_8916.priv = pll_res;
dsi_vco_clk_8916.priv = pll_res;
pll_res->vco_delay = VCO_DELAY_USEC;
/* Set clock source operations */
pixel_clk_src_ops = clk_ops_slave_div;
pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
analog_postdiv_clk_ops = clk_ops_div;
analog_postdiv_clk_ops.prepare = dsi_pll_div_prepare;
byte_clk_src_ops = clk_ops_div;
byte_clk_src_ops.prepare = dsi_pll_div_prepare;
byte_mux_clk_ops = clk_ops_gen_mux;
byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;
if (pll_res->target_id == MDSS_PLL_TARGET_8916 ||
pll_res->target_id == MDSS_PLL_TARGET_8939 ||
pll_res->target_id == MDSS_PLL_TARGET_8909) {
rc = of_msm_clock_register(pdev->dev.of_node,
mdss_dsi_pllcc_8916, ARRAY_SIZE(mdss_dsi_pllcc_8916));
if (rc) {
pr_err("Clock register failed\n");
rc = -EPROBE_DEFER;
}
} else {
pr_err("Invalid target ID\n");
rc = -EINVAL;
}
if (!rc)
pr_info("Registered DSI PLL clocks successfully\n");
return rc;
}

588
drivers/clk/msm/mdss/mdss-dsi-pll-util.c
View file

@ -1,588 +0,0 @@
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/iopoll.h>
#include <linux/delay.h>
#include <linux/clk/msm-clock-generic.h>
#include "mdss-pll.h"
#include "mdss-dsi-pll.h"
#define DSI_PHY_PLL_UNIPHY_PLL_REFCLK_CFG (0x0)
#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG (0x0004)
#define DSI_PHY_PLL_UNIPHY_PLL_CHGPUMP_CFG (0x0008)
#define DSI_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG (0x000C)
#define DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG (0x0010)
#define DSI_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG (0x0014)
#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG (0x0024)
#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG (0x0028)
#define DSI_PHY_PLL_UNIPHY_PLL_LPFR_CFG (0x002C)
#define DSI_PHY_PLL_UNIPHY_PLL_LPFC1_CFG (0x0030)
#define DSI_PHY_PLL_UNIPHY_PLL_LPFC2_CFG (0x0034)
#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0 (0x0038)
#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG1 (0x003C)
#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG2 (0x0040)
#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG3 (0x0044)
#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG4 (0x0048)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG0 (0x006C)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG2 (0x0074)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG3 (0x0078)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG4 (0x007C)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG5 (0x0080)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG6 (0x0084)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG7 (0x0088)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG8 (0x008C)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG9 (0x0090)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG10 (0x0094)
#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG11 (0x0098)
#define DSI_PHY_PLL_UNIPHY_PLL_EFUSE_CFG (0x009C)
#define DSI_PHY_PLL_UNIPHY_PLL_STATUS (0x00C0)
#define DSI_PLL_POLL_DELAY_US 50
#define DSI_PLL_POLL_TIMEOUT_US 500
int set_byte_mux_sel(struct mux_clk *clk, int sel)
{
struct mdss_pll_resources *dsi_pll_res = clk->priv;
pr_debug("byte mux set to %s mode\n", sel ? "indirect" : "direct");
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG, (sel << 1));
return 0;
}
int get_byte_mux_sel(struct mux_clk *clk)
{
int mux_mode, rc;
struct mdss_pll_resources *dsi_pll_res = clk->priv;
if (is_gdsc_disabled(dsi_pll_res))
return 0;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
mux_mode = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG) & BIT(1);
pr_debug("byte mux mode = %s", mux_mode ? "indirect" : "direct");
mdss_pll_resource_enable(dsi_pll_res, false);
return !!mux_mode;
}
int dsi_pll_div_prepare(struct clk *c)
{
struct div_clk *div = to_div_clk(c);
/* Restore the divider's value */
return div->ops->set_div(div, div->data.div);
}
int dsi_pll_mux_prepare(struct clk *c)
{
struct mux_clk *mux = to_mux_clk(c);
int i, rc, sel = 0;
struct mdss_pll_resources *dsi_pll_res = mux->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
for (i = 0; i < mux->num_parents; i++)
if (mux->parents[i].src == c->parent) {
sel = mux->parents[i].sel;
break;
}
if (i == mux->num_parents) {
pr_err("Failed to select the parent clock\n");
rc = -EINVAL;
goto error;
}
/* Restore the mux source select value */
rc = mux->ops->set_mux_sel(mux, sel);
error:
mdss_pll_resource_enable(dsi_pll_res, false);
return rc;
}
int fixed_4div_set_div(struct div_clk *clk, int div)
{
int rc;
struct mdss_pll_resources *dsi_pll_res = clk->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG, (div - 1));
mdss_pll_resource_enable(dsi_pll_res, false);
return rc;
}
int fixed_4div_get_div(struct div_clk *clk)
{
int div = 0, rc;
struct mdss_pll_resources *dsi_pll_res = clk->priv;
if (is_gdsc_disabled(dsi_pll_res))
return 0;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG);
mdss_pll_resource_enable(dsi_pll_res, false);
return div + 1;
}
int digital_set_div(struct div_clk *clk, int div)
{
int rc;
struct mdss_pll_resources *dsi_pll_res = clk->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, (div - 1));
mdss_pll_resource_enable(dsi_pll_res, false);
return rc;
}
int digital_get_div(struct div_clk *clk)
{
int div = 0, rc;
struct mdss_pll_resources *dsi_pll_res = clk->priv;
if (is_gdsc_disabled(dsi_pll_res))
return 0;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG);
mdss_pll_resource_enable(dsi_pll_res, false);
return div + 1;
}
int analog_set_div(struct div_clk *clk, int div)
{
int rc;
struct mdss_pll_resources *dsi_pll_res = clk->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, div - 1);
mdss_pll_resource_enable(dsi_pll_res, false);
return rc;
}
int analog_get_div(struct div_clk *clk)
{
int div = 0, rc;
struct mdss_pll_resources *dsi_pll_res = clk->priv;
if (is_gdsc_disabled(dsi_pll_res))
return 0;
rc = mdss_pll_resource_enable(clk->priv, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG) + 1;
mdss_pll_resource_enable(dsi_pll_res, false);
return div;
}
int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res)
{
u32 status;
int pll_locked;
/* poll for PLL ready status */
if (readl_poll_timeout_atomic((dsi_pll_res->pll_base +
DSI_PHY_PLL_UNIPHY_PLL_STATUS),
status,
((status & BIT(0)) == 1),
DSI_PLL_POLL_DELAY_US,
DSI_PLL_POLL_TIMEOUT_US)) {
pr_debug("DSI PLL status=%x failed to Lock\n", status);
pll_locked = 0;
} else {
pll_locked = 1;
}
return pll_locked;
}
int vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate)
{
s64 vco_clk_rate = rate;
s32 rem;
s64 refclk_cfg, frac_n_mode, ref_doubler_en_b;
s64 ref_clk_to_pll, div_fbx1000, frac_n_value;
s64 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
s64 gen_vco_clk, cal_cfg10, cal_cfg11;
u32 res;
int i;
struct mdss_pll_resources *dsi_pll_res = vco->priv;
/* Configure the Loop filter resistance */
for (i = 0; i < vco->lpfr_lut_size; i++)
if (vco_clk_rate <= vco->lpfr_lut[i].vco_rate)
break;
if (i == vco->lpfr_lut_size) {
pr_err("unable to get loop filter resistance. vco=%ld\n", rate);
return -EINVAL;
}
res = vco->lpfr_lut[i].r;
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LPFR_CFG, res);
/* Loop filter capacitance values : c1 and c2 */
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LPFC1_CFG, 0x70);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LPFC2_CFG, 0x15);
div_s64_rem(vco_clk_rate, vco->ref_clk_rate, &rem);
if (rem) {
refclk_cfg = 0x1;
frac_n_mode = 1;
ref_doubler_en_b = 0;
} else {
refclk_cfg = 0x0;
frac_n_mode = 0;
ref_doubler_en_b = 1;
}
pr_debug("refclk_cfg = %lld\n", refclk_cfg);
ref_clk_to_pll = ((vco->ref_clk_rate * 2 * (refclk_cfg))
+ (ref_doubler_en_b * vco->ref_clk_rate));
div_fbx1000 = div_s64((vco_clk_rate * 1000), ref_clk_to_pll);
div_s64_rem(div_fbx1000, 1000, &rem);
frac_n_value = div_s64((rem * (1 << 16)), 1000);
gen_vco_clk = div_s64(div_fbx1000 * ref_clk_to_pll, 1000);
pr_debug("ref_clk_to_pll = %lld\n", ref_clk_to_pll);
pr_debug("div_fb = %lld\n", div_fbx1000);
pr_debug("frac_n_value = %lld\n", frac_n_value);
pr_debug("Generated VCO Clock: %lld\n", gen_vco_clk);
rem = 0;
if (frac_n_mode) {
sdm_cfg0 = (0x0 << 5);
sdm_cfg0 |= (0x0 & 0x3f);
sdm_cfg1 = (div_s64(div_fbx1000, 1000) & 0x3f) - 1;
sdm_cfg3 = div_s64_rem(frac_n_value, 256, &rem);
sdm_cfg2 = rem;
} else {
sdm_cfg0 = (0x1 << 5);
sdm_cfg0 |= (div_s64(div_fbx1000, 1000) & 0x3f) - 1;
sdm_cfg1 = (0x0 & 0x3f);
sdm_cfg2 = 0;
sdm_cfg3 = 0;
}
pr_debug("sdm_cfg0=%lld\n", sdm_cfg0);
pr_debug("sdm_cfg1=%lld\n", sdm_cfg1);
pr_debug("sdm_cfg2=%lld\n", sdm_cfg2);
pr_debug("sdm_cfg3=%lld\n", sdm_cfg3);
cal_cfg11 = div_s64_rem(gen_vco_clk, 256 * 1000000, &rem);
cal_cfg10 = rem / 1000000;
pr_debug("cal_cfg10=%lld, cal_cfg11=%lld\n", cal_cfg10, cal_cfg11);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CHGPUMP_CFG, 0x02);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG3, 0x2b);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG4, 0x66);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG1, (u32)(sdm_cfg1 & 0xff));
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG2, (u32)(sdm_cfg2 & 0xff));
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG3, (u32)(sdm_cfg3 & 0xff));
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
/* Add hardware recommended delay for correct PLL configuration */
if (dsi_pll_res->vco_delay)
udelay(dsi_pll_res->vco_delay);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, (u32)refclk_cfg);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG, 0x71);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0, (u32)sdm_cfg0);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x30);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x00);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x00);
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG10, (u32)(cal_cfg10 & 0xff));
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG11, (u32)(cal_cfg11 & 0xff));
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_EFUSE_CFG, 0x20);
return 0;
}
unsigned long vco_get_rate(struct clk *c)
{
u32 sdm0, doubler, sdm_byp_div;
u64 vco_rate;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
u64 ref_clk = vco->ref_clk_rate;
int rc;
struct mdss_pll_resources *dsi_pll_res = vco->priv;
if (is_gdsc_disabled(dsi_pll_res))
return 0;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
/* Check to see if the ref clk doubler is enabled */
doubler = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_REFCLK_CFG) & BIT(0);
ref_clk += (doubler * vco->ref_clk_rate);
/* see if it is integer mode or sdm mode */
sdm0 = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0);
if (sdm0 & BIT(6)) {
/* integer mode */
sdm_byp_div = (MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0) & 0x3f) + 1;
vco_rate = ref_clk * sdm_byp_div;
} else {
/* sdm mode */
sdm_dc_off = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG1) & 0xFF;
pr_debug("sdm_dc_off = %d\n", sdm_dc_off);
sdm2 = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG2) & 0xFF;
sdm3 = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG3) & 0xFF;
sdm_freq_seed = (sdm3 << 8) | sdm2;
pr_debug("sdm_freq_seed = %d\n", sdm_freq_seed);
vco_rate = (ref_clk * (sdm_dc_off + 1)) +
mult_frac(ref_clk, sdm_freq_seed, BIT(16));
pr_debug("vco rate = %lld", vco_rate);
}
pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate);
mdss_pll_resource_enable(dsi_pll_res, false);
return (unsigned long)vco_rate;
}
static int dsi_pll_enable(struct clk *c)
{
int i, rc;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return rc;
}
/* Try all enable sequences until one succeeds */
for (i = 0; i < vco->pll_en_seq_cnt; i++) {
rc = vco->pll_enable_seqs[i](dsi_pll_res);
pr_debug("DSI PLL %s after sequence #%d\n",
rc ? "unlocked" : "locked", i + 1);
if (!rc)
break;
}
if (rc) {
mdss_pll_resource_enable(dsi_pll_res, false);
pr_err("DSI PLL failed to lock\n");
}
dsi_pll_res->pll_on = true;
return rc;
}
static void dsi_pll_disable(struct clk *c)
{
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
if (!dsi_pll_res->pll_on &&
mdss_pll_resource_enable(dsi_pll_res, true)) {
pr_err("Failed to enable mdss dsi pll resources\n");
return;
}
dsi_pll_res->handoff_resources = false;
MDSS_PLL_REG_W(dsi_pll_res->pll_base,
DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x00);
mdss_pll_resource_enable(dsi_pll_res, false);
dsi_pll_res->pll_on = false;
pr_debug("DSI PLL Disabled\n");
return;
}
long vco_round_rate(struct clk *c, unsigned long rate)
{
unsigned long rrate = rate;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
if (rate < vco->min_rate)
rrate = vco->min_rate;
if (rate > vco->max_rate)
rrate = vco->max_rate;
return rrate;
}
enum handoff vco_handoff(struct clk *c)
{
int rc;
enum handoff ret = HANDOFF_DISABLED_CLK;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
if (is_gdsc_disabled(dsi_pll_res))
return HANDOFF_DISABLED_CLK;
rc = mdss_pll_resource_enable(dsi_pll_res, true);
if (rc) {
pr_err("Failed to enable mdss dsi pll resources\n");
return ret;
}
if (dsi_pll_lock_status(dsi_pll_res)) {
dsi_pll_res->handoff_resources = true;
dsi_pll_res->pll_on = true;
c->rate = vco_get_rate(c);
ret = HANDOFF_ENABLED_CLK;
} else {
mdss_pll_resource_enable(dsi_pll_res, false);
}
return ret;
}
int vco_prepare(struct clk *c)
{
int rc = 0;
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
if (!dsi_pll_res) {
pr_err("Dsi pll resources are not available\n");
return -EINVAL;
}
if ((dsi_pll_res->vco_cached_rate != 0)
&& (dsi_pll_res->vco_cached_rate == c->rate)) {
rc = c->ops->set_rate(c, dsi_pll_res->vco_cached_rate);
if (rc) {
pr_err("vco_set_rate failed. rc=%d\n", rc);
goto error;
}
}
rc = dsi_pll_enable(c);
error:
return rc;
}
void vco_unprepare(struct clk *c)
{
struct dsi_pll_vco_clk *vco = to_vco_clk(c);
struct mdss_pll_resources *dsi_pll_res = vco->priv;
if (!dsi_pll_res) {
pr_err("Dsi pll resources are not available\n");
return;
}
dsi_pll_res->vco_cached_rate = c->rate;
dsi_pll_disable(c);
}

8
drivers/clk/msm/mdss/mdss-dsi-pll.h
View file

@ -50,6 +50,13 @@ static inline struct dsi_pll_vco_clk *to_vco_clk(struct clk *clk)
return container_of(clk, struct dsi_pll_vco_clk, c);
}
static inline int dsi_pll_div_prepare(struct clk *c)
{
struct div_clk *div = to_div_clk(c);
/* Restore the divider's value */
return div->ops->set_div(div, div->data.div);
}
int dsi_pll_clock_register_hpm(struct platform_device *pdev,
struct mdss_pll_resources *pll_res);
int dsi_pll_clock_register_20nm(struct platform_device *pdev,
@ -61,7 +68,6 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
int set_byte_mux_sel(struct mux_clk *clk, int sel);
int get_byte_mux_sel(struct mux_clk *clk);
int dsi_pll_div_prepare(struct clk *c);
int dsi_pll_mux_prepare(struct clk *c);
int fixed_4div_set_div(struct div_clk *clk, int div);
int fixed_4div_get_div(struct div_clk *clk);

594
drivers/clk/msm/mdss/mdss-edp-pll-28hpm.c
View file

@ -1,594 +0,0 @@
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/clk/msm-clk-provider.h>
#include <linux/clk/msm-clk.h>
#include <linux/clk/msm-clock-generic.h>
#include <dt-bindings/clock/msm-clocks-8974.h>
#include "mdss-pll.h"
#include "mdss-edp-pll.h"
#define EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG (0x0)
#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG (0x0004)
#define EDP_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG (0x000C)
#define EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG (0x0020)
#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG (0x0024)
#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG (0x0028)
#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0 (0x0038)
#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1 (0x003C)
#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2 (0x0040)
#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3 (0x0044)
#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4 (0x0048)
#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0 (0x004C)
#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1 (0x0050)
#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2 (0x0054)
#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3 (0x0058)
#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2 (0x0064)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0 (0x006C)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2 (0x0074)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6 (0x0084)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7 (0x0088)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8 (0x008C)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9 (0x0090)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10 (0x0094)
#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11 (0x0098)
#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0 (0x005C)
#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1 (0x0060)
#define EDP_PLL_POLL_DELAY_US 50
#define EDP_PLL_POLL_TIMEOUT_US 500
static struct clk_ops edp_mainlink_clk_src_ops;
static struct clk_div_ops fixed_5div_ops; /* null ops */
static struct clk_ops edp_pixel_clk_ops;
static inline struct edp_pll_vco_clk *to_edp_vco_clk(struct clk *clk)
{
return container_of(clk, struct edp_pll_vco_clk, c);
}
int edp_div_prepare(struct clk *c)
{
struct div_clk *div = to_div_clk(c);
/* Restore the divider's value */
return div->ops->set_div(div, div->data.div);
}
static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate)
{
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
struct mdss_pll_resources *edp_pll_res = vco->priv;
int rc;
pr_debug("vco_rate=%d\n", (int)vco_rate);
rc = mdss_pll_resource_enable(edp_pll_res, true);
if (rc) {
pr_err("failed to enable edp pll res rc=%d\n", rc);
rc = -EINVAL;
}
if (vco_rate == 810000000) {
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG, 0x18);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0, 0x36);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1, 0x69);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2, 0xff);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3, 0x2f);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0, 0x80);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x5a);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x0);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x0);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10, 0x2a);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11, 0x3);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0, 0x10);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1, 0x1a);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, 0x00);
} else if (vco_rate == 1350000000) {
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x01);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0, 0x36);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1, 0x62);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3, 0x28);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0, 0x80);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x5a);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x0);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x0);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10, 0x46);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11, 0x5);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0, 0x10);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1, 0x1a);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, 0x00);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, 0x00);
} else {
pr_err("rate=%d is NOT supported\n", (int)vco_rate);
vco_rate = 0;
rc = -EINVAL;
}
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
udelay(100);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
udelay(100);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
udelay(100);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
udelay(100);
mdss_pll_resource_enable(edp_pll_res, false);
vco->rate = vco_rate;
return rc;
}
static int edp_pll_ready_poll(struct mdss_pll_resources *edp_pll_res)
{
int cnt;
u32 status;
cnt = 100;
while (cnt--) {
udelay(100);
status = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0xc0);
status &= 0x01;
if (status)
break;
}
pr_debug("cnt=%d status=%d\n", cnt, (int)status);
if (status)
return 1;
return 0;
}
static int edp_vco_enable(struct clk *c)
{
int i, ready;
int rc;
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
struct mdss_pll_resources *edp_pll_res = vco->priv;
rc = mdss_pll_resource_enable(edp_pll_res, true);
if (rc) {
pr_err("edp pll resources not available\n");
return rc;
}
for (i = 0; i < 3; i++) {
ready = edp_pll_ready_poll(edp_pll_res);
if (ready)
break;
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
udelay(100);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
udelay(100);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
udelay(100);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
udelay(100);
}
if (ready) {
pr_debug("EDP PLL lock success\n");
edp_pll_res->pll_on = true;
rc = 0;
} else {
pr_err("EDP PLL failed to lock\n");
mdss_pll_resource_enable(edp_pll_res, false);
rc = -EINVAL;
}
return rc;
}
static void edp_vco_disable(struct clk *c)
{
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
struct mdss_pll_resources *edp_pll_res = vco->priv;
if (!edp_pll_res) {
pr_err("Invalid input parameter\n");
return;
}
if (!edp_pll_res->pll_on &&
mdss_pll_resource_enable(edp_pll_res, true)) {
pr_err("edp pll resources not available\n");
return;
}
MDSS_PLL_REG_W(edp_pll_res->pll_base, 0x20, 0x00);
edp_pll_res->handoff_resources = false;
edp_pll_res->pll_on = false;
mdss_pll_resource_enable(edp_pll_res, false);
pr_debug("EDP PLL Disabled\n");
return;
}
static unsigned long edp_vco_get_rate(struct clk *c)
{
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
struct mdss_pll_resources *edp_pll_res = vco->priv;
u32 pll_status, div2;
int rc;
if (is_gdsc_disabled(edp_pll_res))
return 0;
rc = mdss_pll_resource_enable(edp_pll_res, true);
if (rc) {
pr_err("edp pll resources not available\n");
return rc;
}
if (vco->rate == 0) {
pll_status = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0xc0);
if (pll_status & 0x01) {
div2 = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0x24);
if (div2 & 0x01)
vco->rate = 1350000000;
else
vco->rate = 810000000;
}
}
mdss_pll_resource_enable(edp_pll_res, false);
pr_debug("rate=%d\n", (int)vco->rate);
return vco->rate;
}
static long edp_vco_round_rate(struct clk *c, unsigned long rate)
{
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
unsigned long rrate = -ENOENT;
unsigned long *lp;
lp = vco->rate_list;
while (*lp) {
rrate = *lp;
if (rate <= rrate)
break;
lp++;
}
pr_debug("rrate=%d\n", (int)rrate);
return rrate;
}
static int edp_vco_prepare(struct clk *c)
{
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
pr_debug("rate=%d\n", (int)vco->rate);
return edp_vco_set_rate(c, vco->rate);
}
static void edp_vco_unprepare(struct clk *c)
{
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
pr_debug("rate=%d\n", (int)vco->rate);
edp_vco_disable(c);
}
static int edp_pll_lock_status(struct mdss_pll_resources *edp_pll_res)
{
u32 status;
int pll_locked = 0;
int rc;
rc = mdss_pll_resource_enable(edp_pll_res, true);
if (rc) {
pr_err("edp pll resources not available\n");
return rc;
}
/* poll for PLL ready status */
if (readl_poll_timeout_atomic((edp_pll_res->pll_base + 0xc0),
status, ((status & BIT(0)) == 1),
EDP_PLL_POLL_DELAY_US,
EDP_PLL_POLL_TIMEOUT_US)) {
pr_debug("EDP PLL status=%x failed to Lock\n", status);
pll_locked = 0;
} else {
pll_locked = 1;
}
mdss_pll_resource_enable(edp_pll_res, false);
return pll_locked;
}
static enum handoff edp_vco_handoff(struct clk *c)
{
enum handoff ret = HANDOFF_DISABLED_CLK;
struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
struct mdss_pll_resources *edp_pll_res = vco->priv;
if (is_gdsc_disabled(edp_pll_res))
return HANDOFF_DISABLED_CLK;
if (mdss_pll_resource_enable(edp_pll_res, true)) {
pr_err("edp pll resources not available\n");
return ret;
}
edp_pll_res->handoff_resources = true;
if (edp_pll_lock_status(edp_pll_res)) {
c->rate = edp_vco_get_rate(c);
edp_pll_res->pll_on = true;
ret = HANDOFF_ENABLED_CLK;
} else {
edp_pll_res->handoff_resources = false;
mdss_pll_resource_enable(edp_pll_res, false);
}
pr_debug("done, ret=%d\n", ret);
return ret;
}
static unsigned long edp_vco_rate_list[] = {
810000000, 1350000000, 0};
struct clk_ops edp_vco_clk_ops = {
.enable = edp_vco_enable,
.set_rate = edp_vco_set_rate,
.get_rate = edp_vco_get_rate,
.round_rate = edp_vco_round_rate,
.prepare = edp_vco_prepare,
.unprepare = edp_vco_unprepare,
.handoff = edp_vco_handoff,
};
struct edp_pll_vco_clk edp_vco_clk = {
.ref_clk_rate = 19200000,
.rate = 0,
.rate_list = edp_vco_rate_list,
.c = {
.dbg_name = "edp_vco_clk",
.ops = &edp_vco_clk_ops,
CLK_INIT(edp_vco_clk.c),
},
};
static unsigned long edp_mainlink_get_rate(struct clk *c)
{
struct div_clk *mclk = to_div_clk(c);
struct clk *pclk;
unsigned long rate = 0;
pclk = clk_get_parent(c);
if (pclk && pclk->ops->get_rate) {
rate = pclk->ops->get_rate(pclk);
rate /= mclk->data.div;
}
pr_debug("rate=%d div=%d\n", (int)rate, mclk->data.div);
return rate;
}
struct div_clk edp_mainlink_clk_src = {
.ops = &fixed_5div_ops,
.data = {
.div = 5,
.min_div = 5,
.max_div = 5,
},
.c = {
.parent = &edp_vco_clk.c,
.dbg_name = "edp_mainlink_clk_src",
.ops = &edp_mainlink_clk_src_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(edp_mainlink_clk_src.c),
}
};
/*
* this rate is from pll to clock controller
* output from pll to CC has two possibilities
* 1: if mainlink rate is 270M, then 675M
* 2: if mainlink rate is 162M, then 810M
*/
static int edp_pixel_set_div(struct div_clk *clk, int div)
{
int rc;
struct mdss_pll_resources *edp_pll_res = clk->priv;
rc = mdss_pll_resource_enable(edp_pll_res, true);
if (rc) {
pr_err("edp pll resources not available\n");
return rc;
}
pr_debug("div=%d\n", div);
MDSS_PLL_REG_W(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG, (div - 1));
mdss_pll_resource_enable(edp_pll_res, false);
return 0;
}
static int edp_pixel_get_div(struct div_clk *clk)
{
int div = 0;
int rc;
struct mdss_pll_resources *edp_pll_res = clk->priv;
if (is_gdsc_disabled(edp_pll_res))
return 0;
rc = mdss_pll_resource_enable(edp_pll_res, true);
if (rc) {
pr_err("edp pll resources not available\n");
return rc;
}
div = MDSS_PLL_REG_R(edp_pll_res->pll_base,
EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG);
mdss_pll_resource_enable(edp_pll_res, false);
div &= 0x01;
pr_debug("div=%d\n", div);
return div + 1;
}
static struct clk_div_ops edp_pixel_ops = {
.set_div = edp_pixel_set_div,
.get_div = edp_pixel_get_div,
};
struct div_clk edp_pixel_clk_src = {
.data = {
.max_div = 2,
.min_div = 1,
},
.ops = &edp_pixel_ops,
.c = {
.parent = &edp_vco_clk.c,
.dbg_name = "edp_pixel_clk_src",
.ops = &edp_pixel_clk_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(edp_pixel_clk_src.c),
},
};
static struct clk_lookup mdss_edp_pllcc_8974[] = {
CLK_LOOKUP("edp_pixel_src", edp_pixel_clk_src.c,
"fd8c0000.qcom,mmsscc-mdss"),
CLK_LOOKUP("edp_mainlink_src", edp_mainlink_clk_src.c,
"fd8c0000.qcom,mmsscc-mdss"),
};
int edp_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc = -ENOTSUPP;
if (!pll_res || !pll_res->pll_base) {
pr_err("Invalid input parameters\n");
return -EPROBE_DEFER;
}
/* Set client data to div and vco clocks */
edp_pixel_clk_src.priv = pll_res;
edp_mainlink_clk_src.priv = pll_res;
edp_vco_clk.priv = pll_res;
/* Set clock operation for mainlink and pixel clock */
edp_mainlink_clk_src_ops = clk_ops_div;
edp_mainlink_clk_src_ops.get_parent = clk_get_parent;
edp_mainlink_clk_src_ops.get_rate = edp_mainlink_get_rate;
edp_pixel_clk_ops = clk_ops_slave_div;
edp_pixel_clk_ops.prepare = edp_div_prepare;
rc = of_msm_clock_register(pdev->dev.of_node, mdss_edp_pllcc_8974,
ARRAY_SIZE(mdss_edp_pllcc_8974));
if (rc) {
pr_err("Clock register failed rc=%d\n", rc);
rc = -EPROBE_DEFER;
}
return rc;
}

27
drivers/clk/msm/mdss/mdss-edp-pll.h
View file

@ -1,27 +0,0 @@
/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MDSS_EDP_PLL_H
#define __MDSS_EDP_PLL_H
struct edp_pll_vco_clk {
unsigned long ref_clk_rate;
unsigned long rate; /* vco rate */
unsigned long *rate_list;
void *priv;
struct clk c;
};
int edp_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res);
#endif

974
drivers/clk/msm/mdss/mdss-hdmi-pll-20nm.c
View file

@ -1,974 +0,0 @@
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/clk/msm-clk-provider.h>
#include <linux/clk/msm-clk.h>
#include <linux/clk/msm-clock-generic.h>
#include <dt-bindings/clock/msm-clocks-8994.h>
#include "mdss-pll.h"
#include "mdss-hdmi-pll.h"
/* hdmi phy registers */
#define HDMI_PHY_CMD_SIZE 68
#define HDMI_PHY_CLK_SIZE 97
/* Set to 1 for auto KVCO cal; set to 0 for fixed value */
#define HDMI_PHY_AUTO_KVCO_CAL 1
/* PLL REGISTERS */
#define QSERDES_COM_SYS_CLK_CTRL (0x000)
#define QSERDES_COM_PLL_VCOTAIL_EN (0x004)
#define QSERDES_COM_CMN_MODE (0x008)
#define QSERDES_COM_IE_TRIM (0x00C)
#define QSERDES_COM_IP_TRIM (0x010)
#define QSERDES_COM_PLL_CNTRL (0x014)
#define QSERDES_COM_PLL_PHSEL_CONTROL (0x018)
#define QSERDES_COM_IPTAT_TRIM_VCCA_TX_SEL (0x01C)
#define QSERDES_COM_PLL_PHSEL_DC (0x020)
#define QSERDES_COM_PLL_IP_SETI (0x024)
#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL (0x028)
#define QSERDES_COM_PLL_BKG_KVCO_CAL_EN (0x02C)
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x030)
#define QSERDES_COM_PLL_CP_SETI (0x034)
#define QSERDES_COM_PLL_IP_SETP (0x038)
#define QSERDES_COM_PLL_CP_SETP (0x03C)
#define QSERDES_COM_ATB_SEL1 (0x040)
#define QSERDES_COM_ATB_SEL2 (0x044)
#define QSERDES_COM_SYSCLK_EN_SEL_TXBAND (0x048)
#define QSERDES_COM_RESETSM_CNTRL (0x04C)
#define QSERDES_COM_RESETSM_CNTRL2 (0x050)
#define QSERDES_COM_RESETSM_CNTRL3 (0x054)
#define QSERDES_COM_RESETSM_PLL_CAL_COUNT1 (0x058)
#define QSERDES_COM_RESETSM_PLL_CAL_COUNT2 (0x05C)
#define QSERDES_COM_DIV_REF1 (0x060)
#define QSERDES_COM_DIV_REF2 (0x064)
#define QSERDES_COM_KVCO_COUNT1 (0x068)
#define QSERDES_COM_KVCO_COUNT2 (0x06C)
#define QSERDES_COM_KVCO_CAL_CNTRL (0x070)
#define QSERDES_COM_KVCO_CODE (0x074)
#define QSERDES_COM_VREF_CFG1 (0x078)
#define QSERDES_COM_VREF_CFG2 (0x07C)
#define QSERDES_COM_VREF_CFG3 (0x080)
#define QSERDES_COM_VREF_CFG4 (0x084)
#define QSERDES_COM_VREF_CFG5 (0x088)
#define QSERDES_COM_VREF_CFG6 (0x08C)
#define QSERDES_COM_PLLLOCK_CMP1 (0x090)
#define QSERDES_COM_PLLLOCK_CMP2 (0x094)
#define QSERDES_COM_PLLLOCK_CMP3 (0x098)
#define QSERDES_COM_PLLLOCK_CMP_EN (0x09C)
#define QSERDES_COM_BGTC (0x0A0)
#define QSERDES_COM_PLL_TEST_UPDN (0x0A4)
#define QSERDES_COM_PLL_VCO_TUNE (0x0A8)
#define QSERDES_COM_DEC_START1 (0x0AC)
#define QSERDES_COM_PLL_AMP_OS (0x0B0)
#define QSERDES_COM_SSC_EN_CENTER (0x0B4)
#define QSERDES_COM_SSC_ADJ_PER1 (0x0B8)
#define QSERDES_COM_SSC_ADJ_PER2 (0x0BC)
#define QSERDES_COM_SSC_PER1 (0x0C0)
#define QSERDES_COM_SSC_PER2 (0x0C4)
#define QSERDES_COM_SSC_STEP_SIZE1 (0x0C8)
#define QSERDES_COM_SSC_STEP_SIZE2 (0x0CC)
#define QSERDES_COM_RES_CODE_UP (0x0D0)
#define QSERDES_COM_RES_CODE_DN (0x0D4)
#define QSERDES_COM_RES_CODE_UP_OFFSET (0x0D8)
#define QSERDES_COM_RES_CODE_DN_OFFSET (0x0DC)
#define QSERDES_COM_RES_CODE_START_SEG1 (0x0E0)
#define QSERDES_COM_RES_CODE_START_SEG2 (0x0E4)
#define QSERDES_COM_RES_CODE_CAL_CSR (0x0E8)
#define QSERDES_COM_RES_CODE (0x0EC)
#define QSERDES_COM_RES_TRIM_CONTROL (0x0F0)
#define QSERDES_COM_RES_TRIM_CONTROL2 (0x0F4)
#define QSERDES_COM_RES_TRIM_EN_VCOCALDONE (0x0F8)
#define QSERDES_COM_FAUX_EN (0x0FC)
#define QSERDES_COM_DIV_FRAC_START1 (0x100)
#define QSERDES_COM_DIV_FRAC_START2 (0x104)
#define QSERDES_COM_DIV_FRAC_START3 (0x108)
#define QSERDES_COM_DEC_START2 (0x10C)
#define QSERDES_COM_PLL_RXTXEPCLK_EN (0x110)
#define QSERDES_COM_PLL_CRCTRL (0x114)
#define QSERDES_COM_PLL_CLKEPDIV (0x118)
#define QSERDES_COM_PLL_FREQUPDATE (0x11C)
#define QSERDES_COM_PLL_BKGCAL_TRIM_UP (0x120)
#define QSERDES_COM_PLL_BKGCAL_TRIM_DN (0x124)
#define QSERDES_COM_PLL_BKGCAL_TRIM_MUX (0x128)
#define QSERDES_COM_PLL_BKGCAL_VREF_CFG (0x12C)
#define QSERDES_COM_PLL_BKGCAL_DIV_REF1 (0x130)
#define QSERDES_COM_PLL_BKGCAL_DIV_REF2 (0x134)
#define QSERDES_COM_MUXADDR (0x138)
#define QSERDES_COM_LOW_POWER_RO_CONTROL (0x13C)
#define QSERDES_COM_POST_DIVIDER_CONTROL (0x140)
#define QSERDES_COM_HR_OCLK2_DIVIDER (0x144)
#define QSERDES_COM_HR_OCLK3_DIVIDER (0x148)
#define QSERDES_COM_PLL_VCO_HIGH (0x14C)
#define QSERDES_COM_RESET_SM (0x150)
#define QSERDES_COM_MUXVAL (0x154)
#define QSERDES_COM_CORE_RES_CODE_DN (0x158)
#define QSERDES_COM_CORE_RES_CODE_UP (0x15C)
#define QSERDES_COM_CORE_VCO_TUNE (0x160)
#define QSERDES_COM_CORE_VCO_TAIL (0x164)
#define QSERDES_COM_CORE_KVCO_CODE (0x168)
/* Tx Channel 0 REGISTERS */
#define QSERDES_TX_L0_BIST_MODE_LANENO (0x00)
#define QSERDES_TX_L0_CLKBUF_ENABLE (0x04)
#define QSERDES_TX_L0_TX_EMP_POST1_LVL (0x08)
#define QSERDES_TX_L0_TX_DRV_LVL (0x0C)
#define QSERDES_TX_L0_RESET_TSYNC_EN (0x10)
#define QSERDES_TX_L0_LPB_EN (0x14)
#define QSERDES_TX_L0_RES_CODE_UP (0x18)
#define QSERDES_TX_L0_RES_CODE_DN (0x1C)
#define QSERDES_TX_L0_PERL_LENGTH1 (0x20)
#define QSERDES_TX_L0_PERL_LENGTH2 (0x24)
#define QSERDES_TX_L0_SERDES_BYP_EN_OUT (0x28)
#define QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
#define QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN (0x30)
#define QSERDES_TX_L0_BIST_PATTERN1 (0x34)
#define QSERDES_TX_L0_BIST_PATTERN2 (0x38)
#define QSERDES_TX_L0_BIST_PATTERN3 (0x3C)
#define QSERDES_TX_L0_BIST_PATTERN4 (0x40)
#define QSERDES_TX_L0_BIST_PATTERN5 (0x44)
#define QSERDES_TX_L0_BIST_PATTERN6 (0x48)
#define QSERDES_TX_L0_BIST_PATTERN7 (0x4C)
#define QSERDES_TX_L0_BIST_PATTERN8 (0x50)
#define QSERDES_TX_L0_LANE_MODE (0x54)
#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE (0x58)
#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
#define QSERDES_TX_L0_ATB_SEL1 (0x60)
#define QSERDES_TX_L0_ATB_SEL2 (0x64)
#define QSERDES_TX_L0_RCV_DETECT_LVL (0x68)
#define QSERDES_TX_L0_PRBS_SEED1 (0x6C)
#define QSERDES_TX_L0_PRBS_SEED2 (0x70)
#define QSERDES_TX_L0_PRBS_SEED3 (0x74)
#define QSERDES_TX_L0_PRBS_SEED4 (0x78)
#define QSERDES_TX_L0_RESET_GEN (0x7C)
#define QSERDES_TX_L0_TRAN_DRVR_EMP_EN (0x80)
#define QSERDES_TX_L0_TX_INTERFACE_MODE (0x84)
#define QSERDES_TX_L0_PWM_CTRL (0x88)
#define QSERDES_TX_L0_PWM_DATA (0x8C)
#define QSERDES_TX_L0_PWM_ENC_DIV_CTRL (0x90)
#define QSERDES_TX_L0_VMODE_CTRL1 (0x94)
#define QSERDES_TX_L0_VMODE_CTRL2 (0x98)
#define QSERDES_TX_L0_VMODE_CTRL3 (0x9C)
#define QSERDES_TX_L0_VMODE_CTRL4 (0xA0)
#define QSERDES_TX_L0_VMODE_CTRL5 (0xA4)
#define QSERDES_TX_L0_VMODE_CTRL6 (0xA8)
#define QSERDES_TX_L0_VMODE_CTRL7 (0xAC)
#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV_CNTL (0xB0)
#define QSERDES_TX_L0_BIST_STATUS (0xB4)
#define QSERDES_TX_L0_BIST_ERROR_COUNT1 (0xB8)
#define QSERDES_TX_L0_BIST_ERROR_COUNT2 (0xBC)
#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV (0xC0)
#define QSERDES_TX_L0_PWM_DEC_STATUS (0xC4)
/* Tx Channel 1 REGISTERS */
#define QSERDES_TX_L1_BIST_MODE_LANENO (0x00)
#define QSERDES_TX_L1_CLKBUF_ENABLE (0x04)
#define QSERDES_TX_L1_TX_EMP_POST1_LVL (0x08)
#define QSERDES_TX_L1_TX_DRV_LVL (0x0C)
#define QSERDES_TX_L1_RESET_TSYNC_EN (0x10)
#define QSERDES_TX_L1_LPB_EN (0x14)
#define QSERDES_TX_L1_RES_CODE_UP (0x18)
#define QSERDES_TX_L1_RES_CODE_DN (0x1C)
#define QSERDES_TX_L1_PERL_LENGTH1 (0x20)
#define QSERDES_TX_L1_PERL_LENGTH2 (0x24)
#define QSERDES_TX_L1_SERDES_BYP_EN_OUT (0x28)
#define QSERDES_TX_L1_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
#define QSERDES_TX_L1_PARRATE_REC_DETECT_IDLE_EN (0x30)
#define QSERDES_TX_L1_BIST_PATTERN1 (0x34)
#define QSERDES_TX_L1_BIST_PATTERN2 (0x38)
#define QSERDES_TX_L1_BIST_PATTERN3 (0x3C)
#define QSERDES_TX_L1_BIST_PATTERN4 (0x40)
#define QSERDES_TX_L1_BIST_PATTERN5 (0x44)
#define QSERDES_TX_L1_BIST_PATTERN6 (0x48)
#define QSERDES_TX_L1_BIST_PATTERN7 (0x4C)
#define QSERDES_TX_L1_BIST_PATTERN8 (0x50)
#define QSERDES_TX_L1_LANE_MODE (0x54)
#define QSERDES_TX_L1_IDAC_CAL_LANE_MODE (0x58)
#define QSERDES_TX_L1_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
#define QSERDES_TX_L1_ATB_SEL1 (0x60)
#define QSERDES_TX_L1_ATB_SEL2 (0x64)
#define QSERDES_TX_L1_RCV_DETECT_LVL (0x68)
#define QSERDES_TX_L1_PRBS_SEED1 (0x6C)
#define QSERDES_TX_L1_PRBS_SEED2 (0x70)
#define QSERDES_TX_L1_PRBS_SEED3 (0x74)
#define QSERDES_TX_L1_PRBS_SEED4 (0x78)
#define QSERDES_TX_L1_RESET_GEN (0x7C)
#define QSERDES_TX_L1_TRAN_DRVR_EMP_EN (0x80)
#define QSERDES_TX_L1_TX_INTERFACE_MODE (0x84)
#define QSERDES_TX_L1_PWM_CTRL (0x88)
#define QSERDES_TX_L1_PWM_DATA (0x8C)
#define QSERDES_TX_L1_PWM_ENC_DIV_CTRL (0x90)
#define QSERDES_TX_L1_VMODE_CTRL1 (0x94)
#define QSERDES_TX_L1_VMODE_CTRL2 (0x98)
#define QSERDES_TX_L1_VMODE_CTRL3 (0x9C)
#define QSERDES_TX_L1_VMODE_CTRL4 (0xA0)
#define QSERDES_TX_L1_VMODE_CTRL5 (0xA4)
#define QSERDES_TX_L1_VMODE_CTRL6 (0xA8)
#define QSERDES_TX_L1_VMODE_CTRL7 (0xAC)
#define QSERDES_TX_L1_TX_ALOG_INTF_OBSV_CNTL (0xB0)
#define QSERDES_TX_L1_BIST_STATUS (0xB4)
#define QSERDES_TX_L1_BIST_ERROR_COUNT1 (0xB8)
#define QSERDES_TX_L1_BIST_ERROR_COUNT2 (0xBC)
#define QSERDES_TX_L1_TX_ALOG_INTF_OBSV (0xC0)
#define QSERDES_TX_L1_PWM_DEC_STATUS (0xC4)
/* Tx Channel 2 REGISERS */
#define QSERDES_TX_L2_BIST_MODE_LANENO (0x00)
#define QSERDES_TX_L2_CLKBUF_ENABLE (0x04)
#define QSERDES_TX_L2_TX_EMP_POST1_LVL (0x08)
#define QSERDES_TX_L2_TX_DRV_LVL (0x0C)
#define QSERDES_TX_L2_RESET_TSYNC_EN (0x10)
#define QSERDES_TX_L2_LPB_EN (0x14)
#define QSERDES_TX_L2_RES_CODE_UP (0x18)
#define QSERDES_TX_L2_RES_CODE_DN (0x1C)
#define QSERDES_TX_L2_PERL_LENGTH1 (0x20)
#define QSERDES_TX_L2_PERL_LENGTH2 (0x24)
#define QSERDES_TX_L2_SERDES_BYP_EN_OUT (0x28)
#define QSERDES_TX_L2_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
#define QSERDES_TX_L2_PARRATE_REC_DETECT_IDLE_EN (0x30)
#define QSERDES_TX_L2_BIST_PATTERN1 (0x34)
#define QSERDES_TX_L2_BIST_PATTERN2 (0x38)
#define QSERDES_TX_L2_BIST_PATTERN3 (0x3C)
#define QSERDES_TX_L2_BIST_PATTERN4 (0x40)
#define QSERDES_TX_L2_BIST_PATTERN5 (0x44)
#define QSERDES_TX_L2_BIST_PATTERN6 (0x48)
#define QSERDES_TX_L2_BIST_PATTERN7 (0x4C)
#define QSERDES_TX_L2_BIST_PATTERN8 (0x50)
#define QSERDES_TX_L2_LANE_MODE (0x54)
#define QSERDES_TX_L2_IDAC_CAL_LANE_MODE (0x58)
#define QSERDES_TX_L2_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
#define QSERDES_TX_L2_ATB_SEL1 (0x60)
#define QSERDES_TX_L2_ATB_SEL2 (0x64)
#define QSERDES_TX_L2_RCV_DETECT_LVL (0x68)
#define QSERDES_TX_L2_PRBS_SEED1 (0x6C)
#define QSERDES_TX_L2_PRBS_SEED2 (0x70)
#define QSERDES_TX_L2_PRBS_SEED3 (0x74)
#define QSERDES_TX_L2_PRBS_SEED4 (0x78)
#define QSERDES_TX_L2_RESET_GEN (0x7C)
#define QSERDES_TX_L2_TRAN_DRVR_EMP_EN (0x80)
#define QSERDES_TX_L2_TX_INTERFACE_MODE (0x84)
#define QSERDES_TX_L2_PWM_CTRL (0x88)
#define QSERDES_TX_L2_PWM_DATA (0x8C)
#define QSERDES_TX_L2_PWM_ENC_DIV_CTRL (0x90)
#define QSERDES_TX_L2_VMODE_CTRL1 (0x94)
#define QSERDES_TX_L2_VMODE_CTRL2 (0x98)
#define QSERDES_TX_L2_VMODE_CTRL3 (0x9C)
#define QSERDES_TX_L2_VMODE_CTRL4 (0xA0)
#define QSERDES_TX_L2_VMODE_CTRL5 (0xA4)
#define QSERDES_TX_L2_VMODE_CTRL6 (0xA8)
#define QSERDES_TX_L2_VMODE_CTRL7 (0xAC)
#define QSERDES_TX_L2_TX_ALOG_INTF_OBSV_CNTL (0xB0)
#define QSERDES_TX_L2_BIST_STATUS (0xB4)
#define QSERDES_TX_L2_BIST_ERROR_COUNT1 (0xB8)
#define QSERDES_TX_L2_BIST_ERROR_COUNT2 (0xBC)
#define QSERDES_TX_L2_TX_ALOG_INTF_OBSV (0xC0)
#define QSERDES_TX_L2_PWM_DEC_STATUS (0xC4)
/* Tx Channel 3 REGISERS */
#define QSERDES_TX_L3_BIST_MODE_LANENO (0x00)
#define QSERDES_TX_L3_CLKBUF_ENABLE (0x04)
#define QSERDES_TX_L3_TX_EMP_POST1_LVL (0x08)
#define QSERDES_TX_L3_TX_DRV_LVL (0x0C)
#define QSERDES_TX_L3_RESET_TSYNC_EN (0x10)
#define QSERDES_TX_L3_LPB_EN (0x14)
#define QSERDES_TX_L3_RES_CODE_UP (0x18)
#define QSERDES_TX_L3_RES_CODE_DN (0x1C)
#define QSERDES_TX_L3_PERL_LENGTH1 (0x20)
#define QSERDES_TX_L3_PERL_LENGTH2 (0x24)
#define QSERDES_TX_L3_SERDES_BYP_EN_OUT (0x28)
#define QSERDES_TX_L3_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
#define QSERDES_TX_L3_PARRATE_REC_DETECT_IDLE_EN (0x30)
#define QSERDES_TX_L3_BIST_PATTERN1 (0x34)
#define QSERDES_TX_L3_BIST_PATTERN2 (0x38)
#define QSERDES_TX_L3_BIST_PATTERN3 (0x3C)
#define QSERDES_TX_L3_BIST_PATTERN4 (0x40)
#define QSERDES_TX_L3_BIST_PATTERN5 (0x44)
#define QSERDES_TX_L3_BIST_PATTERN6 (0x48)
#define QSERDES_TX_L3_BIST_PATTERN7 (0x4C)
#define QSERDES_TX_L3_BIST_PATTERN8 (0x50)
#define QSERDES_TX_L3_LANE_MODE (0x54)
#define QSERDES_TX_L3_IDAC_CAL_LANE_MODE (0x58)
#define QSERDES_TX_L3_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
#define QSERDES_TX_L3_ATB_SEL1 (0x60)
#define QSERDES_TX_L3_ATB_SEL2 (0x64)
#define QSERDES_TX_L3_RCV_DETECT_LVL (0x68)
#define QSERDES_TX_L3_PRBS_SEED1 (0x6C)
#define QSERDES_TX_L3_PRBS_SEED2 (0x70)
#define QSERDES_TX_L3_PRBS_SEED3 (0x74)
#define QSERDES_TX_L3_PRBS_SEED4 (0x78)
#define QSERDES_TX_L3_RESET_GEN (0x7C)
#define QSERDES_TX_L3_TRAN_DRVR_EMP_EN (0x80)
#define QSERDES_TX_L3_TX_INTERFACE_MODE (0x84)
#define QSERDES_TX_L3_PWM_CTRL (0x88)
#define QSERDES_TX_L3_PWM_DATA (0x8C)
#define QSERDES_TX_L3_PWM_ENC_DIV_CTRL (0x90)
#define QSERDES_TX_L3_VMODE_CTRL1 (0x94)
#define QSERDES_TX_L3_VMODE_CTRL2 (0x98)
#define QSERDES_TX_L3_VMODE_CTRL3 (0x9C)
#define QSERDES_TX_L3_VMODE_CTRL4 (0xA0)
#define QSERDES_TX_L3_VMODE_CTRL5 (0xA4)
#define QSERDES_TX_L3_VMODE_CTRL6 (0xA8)
#define QSERDES_TX_L3_VMODE_CTRL7 (0xAC)
#define QSERDES_TX_L3_TX_ALOG_INTF_OBSV_CNTL (0xB0)
#define QSERDES_TX_L3_BIST_STATUS (0xB4)
#define QSERDES_TX_L3_BIST_ERROR_COUNT1 (0xB8)
#define QSERDES_TX_L3_BIST_ERROR_COUNT2 (0xBC)
#define QSERDES_TX_L3_TX_ALOG_INTF_OBSV (0xC0)
#define QSERDES_TX_L3_PWM_DEC_STATUS (0xC4)
/* HDMI PHY REGISTERS */
#define HDMI_PHY_CFG (0x00)
#define HDMI_PHY_PD_CTL (0x04)
#define HDMI_PHY_MODE (0x08)
#define HDMI_PHY_MISR_CLEAR (0x0C)
#define HDMI_PHY_TX0_TX1_BIST_CFG0 (0x10)
#define HDMI_PHY_TX0_TX1_BIST_CFG1 (0x14)
#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE0 (0x18)
#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE1 (0x1C)
#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE2 (0x20)
#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE3 (0x24)
#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE0 (0x28)
#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE1 (0x2C)
#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE2 (0x30)
#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE3 (0x34)
#define HDMI_PHY_TX2_TX3_BIST_CFG0 (0x38)
#define HDMI_PHY_TX2_TX3_BIST_CFG1 (0x3C)
#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE0 (0x40)
#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE1 (0x44)
#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE2 (0x48)
#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE3 (0x4C)
#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE0 (0x50)
#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE1 (0x54)
#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE2 (0x58)
#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE3 (0x5C)
#define HDMI_PHY_DEBUG_BUS_SEL (0x60)
#define HDMI_PHY_TXCAL_CFG0 (0x64)
#define HDMI_PHY_TXCAL_CFG1 (0x68)
#define HDMI_PHY_TX0_TX1_BIST_STATUS0 (0x6C)
#define HDMI_PHY_TX0_TX1_BIST_STATUS1 (0x70)
#define HDMI_PHY_TX0_TX1_BIST_STATUS2 (0x74)
#define HDMI_PHY_TX2_TX3_BIST_STATUS0 (0x78)
#define HDMI_PHY_TX2_TX3_BIST_STATUS1 (0x7C)
#define HDMI_PHY_TX2_TX3_BIST_STATUS2 (0x80)
#define HDMI_PHY_PRE_MISR_STATUS0 (0x84)
#define HDMI_PHY_PRE_MISR_STATUS1 (0x88)
#define HDMI_PHY_PRE_MISR_STATUS2 (0x8C)
#define HDMI_PHY_PRE_MISR_STATUS3 (0x90)
#define HDMI_PHY_POST_MISR_STATUS0 (0x94)
#define HDMI_PHY_POST_MISR_STATUS1 (0x98)
#define HDMI_PHY_POST_MISR_STATUS2 (0x9C)
#define HDMI_PHY_POST_MISR_STATUS3 (0xA0)
#define HDMI_PHY_STATUS (0xA4)
#define HDMI_PHY_MISC3_STATUS (0xA8)
#define HDMI_PHY_DEBUG_BUS0 (0xAC)
#define HDMI_PHY_DEBUG_BUS1 (0xB0)
#define HDMI_PHY_DEBUG_BUS2 (0xB4)
#define HDMI_PHY_DEBUG_BUS3 (0xB8)
#define HDMI_PHY_REVISION_ID0 (0xBC)
#define HDMI_PHY_REVISION_ID1 (0xC0)
#define HDMI_PHY_REVISION_ID2 (0xC4)
#define HDMI_PHY_REVISION_ID3 (0xC8)
#define HDMI_PLL_POLL_DELAY_US 50
#define HDMI_PLL_POLL_TIMEOUT_US 125000
#define HDMI_PLL_REF_CLK_RATE 192ULL
#define HDMI_PLL_DIVISOR 10000000000ULL
#define HDMI_PLL_DIVISOR_32 100000U
#define HDMI_PLL_MIN_VCO_CLK 160000000ULL
#define HDMI_PLL_TMDS_MAX 800000000U
static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io)
{
u32 status;
int pll_locked = 0;
int phy_ready = 0;
int rc;
rc = mdss_pll_resource_enable(io, true);
if (rc) {
pr_err("pll resource can't be enabled\n");
return rc;
}
/* Poll for C_READY and PHY READY */
pr_debug("%s: Waiting for PHY Ready\n", __func__);
/* poll for PLL ready status */
if (!readl_poll_timeout_atomic(
(io->pll_base + QSERDES_COM_RESET_SM),
status, ((status & BIT(6)) == 1),
HDMI_PLL_POLL_DELAY_US,
HDMI_PLL_POLL_TIMEOUT_US)) {
pr_debug("%s: C READY\n", __func__);
pll_locked = 1;
} else {
pr_debug("%s: C READY TIMEOUT\n", __func__);
pll_locked = 0;
}
/* poll for PHY ready status */
if (pll_locked && !readl_poll_timeout_atomic(
(io->phy_base + HDMI_PHY_STATUS),
status, ((status & BIT(0)) == 1),
HDMI_PLL_POLL_DELAY_US,
HDMI_PLL_POLL_TIMEOUT_US)) {
pr_debug("%s: PHY READY\n", __func__);
phy_ready = 1;
} else {
pr_debug("%s: PHY READY TIMEOUT\n", __func__);
phy_ready = 0;
}
mdss_pll_resource_enable(io, false);
return phy_ready;
}
static inline struct hdmi_pll_vco_clk *to_hdmi_20nm_vco_clk(struct clk *clk)
{
return container_of(clk, struct hdmi_pll_vco_clk, c);
}
static inline u32 hdmi_20nm_phy_pll_vco_reg_val(struct hdmi_pll_cfg *pll_cfg,
u32 tmds_clk)
{
u32 index = 0;
while (pll_cfg[index].vco_rate < HDMI_PLL_TMDS_MAX &&
pll_cfg[index].vco_rate < tmds_clk)
index++;
return pll_cfg[index].reg;
}
static void hdmi_20nm_phy_pll_calc_settings(struct mdss_pll_resources *io,
struct hdmi_pll_vco_clk *vco, u32 vco_clk, u32 tmds_clk)
{
u32 val = 0;
u64 dec_start_val, frac_start_val, pll_lock_cmp;
/* Calculate decimal and fractional values */
dec_start_val = 1000000UL * vco_clk;
do_div(dec_start_val, HDMI_PLL_REF_CLK_RATE);
do_div(dec_start_val, 2U);
frac_start_val = dec_start_val;
do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
frac_start_val *= HDMI_PLL_DIVISOR;
frac_start_val = dec_start_val - frac_start_val;
frac_start_val *= (u64)(2 << 19);
do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
pll_lock_cmp = dec_start_val;
do_div(pll_lock_cmp, 10U);
pll_lock_cmp *= 0x800;
do_div(pll_lock_cmp, HDMI_PLL_DIVISOR_32);
do_div(pll_lock_cmp, HDMI_PLL_DIVISOR_32);
pll_lock_cmp -= 1U;
do_div(dec_start_val, HDMI_PLL_DIVISOR_32);
do_div(dec_start_val, HDMI_PLL_DIVISOR_32);
/* PLL loop bandwidth */
val = hdmi_20nm_phy_pll_vco_reg_val(vco->ip_seti, tmds_clk);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETI, val);
val = hdmi_20nm_phy_pll_vco_reg_val(vco->cp_seti, tmds_clk);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETI, val);
val = hdmi_20nm_phy_pll_vco_reg_val(vco->cp_setp, tmds_clk);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETP, val);
val = hdmi_20nm_phy_pll_vco_reg_val(vco->ip_setp, tmds_clk);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETP, val);
val = hdmi_20nm_phy_pll_vco_reg_val(vco->crctrl, tmds_clk);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CRCTRL, val);
/* PLL calibration */
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START1,
0x80 | (frac_start_val & 0x7F));
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START2,
0x80 | ((frac_start_val >> 7) & 0x7F));
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START3,
0x40 | ((frac_start_val >> 14) & 0x3F));
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START1,
0x80 | (dec_start_val & 0x7F));
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START2,
0x02 | (0x01 & dec_start_val >> 7));
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP1,
pll_lock_cmp & 0xFF);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP2,
(pll_lock_cmp >> 8) & 0xFF);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP3,
(pll_lock_cmp >> 16) & 0xFF);
}
static u32 hdmi_20nm_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
{
u32 tx_band = 0;
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
u64 vco_clk = tmds_clk;
while (vco_clk > 0 && vco_clk < HDMI_PLL_MIN_VCO_CLK) {
tx_band++;
vco_clk *= 2;
}
/* Initially shut down PHY */
pr_debug("%s: Disabling PHY\n", __func__);
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x0);
udelay(1000);
mb();
/* power-up and recommended common block settings */
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x1F);
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x01);
udelay(1000);
mb();
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x07);
udelay(1000);
mb();
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x05);
udelay(1000);
mb();
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x42);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_VCOTAIL_EN, 0x03);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MODE, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_IE_TRIM, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_IP_TRIM, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CNTRL, 0x07);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_PHSEL_CONTROL, 0x04);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_IPTAT_TRIM_VCCA_TX_SEL, 0xA0);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_PHSEL_DC, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_BKG_KVCO_CAL_EN, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x0F);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL1, 0x01);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL2, 0x01);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYSCLK_EN_SEL_TXBAND,
0x4A + (0x10 * tx_band));
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG1, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG2, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BGTC, 0xFF);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_TEST_UPDN, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_VCO_TUNE, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_AMP_OS, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_EN_CENTER, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_UP, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_DN, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_CODE,
tmds_clk > 300000000 ? 0x3F : 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_COUNT1,
tmds_clk > 300000000 ? 0x00 : 0x8A);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_REF1, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_REF2,
tmds_clk > 300000000 ? 0x00 : 0x01);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_CAL_CNTRL,
tmds_clk > 300000000 ? 0x00 : 0x1F);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG3,
tmds_clk > 300000000 ? 0x00 : 0x40);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG4, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG5, 0x10);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESETSM_CNTRL,
tmds_clk > 300000000 ? 0x80 : 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_CAL_CSR, 0x77);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_TRIM_EN_VCOCALDONE, 0x00);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_RXTXEPCLK_EN, 0x0C);
hdmi_20nm_phy_pll_calc_settings(io, vco, vco_clk, tmds_clk);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP_EN, 0x11);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CNTRL, 0x07);
/* Resistor calibration linear search */
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_START_SEG1, 0x60);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_START_SEG2, 0x60);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_TRIM_CONTROL, 0x01);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESETSM_CNTRL2, 0x07);
udelay(1000);
mb();
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_MODE, tx_band);
/* TX lanes (transceivers) power-up sequence */
MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_CLKBUF_ENABLE, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0x600, QSERDES_TX_L1_CLKBUF_ENABLE, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_CLKBUF_ENABLE, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0xA00, QSERDES_TX_L3_CLKBUF_ENABLE, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0x400,
QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0x600,
QSERDES_TX_L1_TRAN_DRVR_EMP_EN, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0x800,
QSERDES_TX_L2_TRAN_DRVR_EMP_EN, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0xA00,
QSERDES_TX_L3_TRAN_DRVR_EMP_EN, 0x03);
MDSS_PLL_REG_W(io->pll_base + 0x400,
QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN , 0x6F);
MDSS_PLL_REG_W(io->pll_base + 0x600,
QSERDES_TX_L1_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN , 0x6F);
MDSS_PLL_REG_W(io->pll_base + 0x800,
QSERDES_TX_L2_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN , 0x6F);
MDSS_PLL_REG_W(io->pll_base + 0xA00,
QSERDES_TX_L3_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN , 0x6F);
MDSS_PLL_REG_W(io->pll_base + 0x400,
QSERDES_TX_L0_TX_EMP_POST1_LVL, 0x0000002F);
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TXCAL_CFG0, 0x000000AF);
MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_VMODE_CTRL1, 0x08);
MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_VMODE_CTRL1, 0x09);
MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_VMODE_CTRL5, 0xA0);
MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_VMODE_CTRL6, 0x01);
MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_VMODE_CTRL5, 0xA0);
MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_VMODE_CTRL6, 0x01);
MDSS_PLL_REG_W(io->pll_base + 0x400,
QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40);
MDSS_PLL_REG_W(io->pll_base + 0x400,
QSERDES_TX_L0_TX_INTERFACE_MODE, 0x00);
MDSS_PLL_REG_W(io->pll_base + 0x600,
QSERDES_TX_L1_PARRATE_REC_DETECT_IDLE_EN, 0x40);
MDSS_PLL_REG_W(io->pll_base + 0x600,
QSERDES_TX_L1_TX_INTERFACE_MODE, 0x00);
MDSS_PLL_REG_W(io->pll_base + 0x800,
QSERDES_TX_L2_PARRATE_REC_DETECT_IDLE_EN, 0x40);
MDSS_PLL_REG_W(io->pll_base + 0x800,
QSERDES_TX_L2_TX_INTERFACE_MODE, 0x00);
MDSS_PLL_REG_W(io->pll_base + 0xA00,
QSERDES_TX_L3_PARRATE_REC_DETECT_IDLE_EN, 0x40);
MDSS_PLL_REG_W(io->pll_base + 0xA00,
QSERDES_TX_L3_TX_INTERFACE_MODE, 0x00);
return 0;
}
static int hdmi_20nm_vco_enable(struct clk *c)
{
u32 ready_poll;
u32 time_out_loop;
/* Hardware recommended timeout iterator */
u32 time_out_max = 50000;
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000000);
udelay(100);
mb();
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000003);
udelay(100);
mb();
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000009);
udelay(100);
mb();
/* Poll for C_READY and PHY READY */
pr_debug("%s: Waiting for PHY Ready\n", __func__);
time_out_loop = 0;
do {
ready_poll = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_RESET_SM);
time_out_loop++;
udelay(10);
} while (((ready_poll & (1 << 6)) == 0) &&
(time_out_loop < time_out_max));
if (time_out_loop >= time_out_max)
pr_err("%s: ERROR: TIMED OUT BEFORE C READY\n", __func__);
else
pr_debug("%s: C READY\n", __func__);
/* Poll for PHY READY */
pr_debug("%s: Waiting for PHY Ready\n", __func__);
time_out_loop = 0;
do {
ready_poll = MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS);
time_out_loop++;
udelay(1);
} while (((ready_poll & 0x1) == 0) && (time_out_loop < time_out_max));
if (time_out_loop >= time_out_max)
pr_err("%s: TIMED OUT BEFORE PHY READY\n", __func__);
else
pr_debug("%s: HDMI PHY READY\n", __func__);
io->pll_on = true;
return 0;
}
static int hdmi_20nm_vco_set_rate(struct clk *c, unsigned long rate)
{
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
void __iomem *pll_base;
void __iomem *phy_base;
unsigned int set_power_dwn = 0;
int rc;
rc = mdss_pll_resource_enable(io, true);
if (rc) {
pr_err("pll resource can't be enabled\n");
return rc;
}
if (io->pll_on)
set_power_dwn = 1;
pll_base = io->pll_base;
phy_base = io->phy_base;
pr_debug("rate=%ld\n", rate);
hdmi_20nm_phy_pll_set_clk_rate(c, rate);
mdss_pll_resource_enable(io, false);
if (set_power_dwn)
hdmi_20nm_vco_enable(c);
vco->rate = rate;
vco->rate_set = true;
return 0;
}
static unsigned long hdmi_20nm_vco_get_rate(struct clk *c)
{
unsigned long freq = 0;
int rc;
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
if (is_gdsc_disabled(io))
return 0;
rc = mdss_pll_resource_enable(io, true);
if (rc) {
pr_err("pll resource can't be enabled\n");
return rc;
}
mdss_pll_resource_enable(io, false);
return freq;
}
static long hdmi_20nm_vco_round_rate(struct clk *c, unsigned long rate)
{
unsigned long rrate = rate;
pr_debug("rrate=%ld\n", rrate);
return rrate;
}
static int hdmi_20nm_vco_prepare(struct clk *c)
{
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
int ret = 0;
pr_debug("rate=%ld\n", vco->rate);
if (!vco->rate_set && vco->rate)
ret = hdmi_20nm_vco_set_rate(c, vco->rate);
if (!ret) {
ret = mdss_pll_resource_enable(io, true);
if (ret)
pr_err("pll resource can't be enabled\n");
}
return ret;
}
static void hdmi_20nm_vco_unprepare(struct clk *c)
{
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
vco->rate_set = false;
if (!io) {
pr_err("Invalid input parameter\n");
return;
}
if (!io->pll_on &&
mdss_pll_resource_enable(io, true)) {
pr_err("pll resource can't be enabled\n");
return;
}
io->handoff_resources = false;
mdss_pll_resource_enable(io, false);
io->pll_on = false;
}
static enum handoff hdmi_20nm_vco_handoff(struct clk *c)
{
enum handoff ret = HANDOFF_DISABLED_CLK;
struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
struct mdss_pll_resources *io = vco->priv;
if (is_gdsc_disabled(io))
return HANDOFF_DISABLED_CLK;
if (mdss_pll_resource_enable(io, true)) {
pr_err("pll resource can't be enabled\n");
return ret;
}
io->handoff_resources = true;
if (hdmi_20nm_pll_lock_status(io)) {
io->pll_on = true;
c->rate = hdmi_20nm_vco_get_rate(c);
ret = HANDOFF_ENABLED_CLK;
} else {
io->handoff_resources = false;
mdss_pll_resource_enable(io, false);
}
pr_debug("done, ret=%d\n", ret);
return ret;
}
static struct clk_ops hdmi_20nm_vco_clk_ops = {
.enable = hdmi_20nm_vco_enable,
.set_rate = hdmi_20nm_vco_set_rate,
.get_rate = hdmi_20nm_vco_get_rate,
.round_rate = hdmi_20nm_vco_round_rate,
.prepare = hdmi_20nm_vco_prepare,
.unprepare = hdmi_20nm_vco_unprepare,
.handoff = hdmi_20nm_vco_handoff,
};
static struct hdmi_pll_vco_clk hdmi_20nm_vco_clk = {
.ip_seti = (struct hdmi_pll_cfg[]){
{550890000, 0x03},
{589240000, 0x07},
{689290000, 0x03},
{727600000, 0x07},
{HDMI_PLL_TMDS_MAX, 0x03},
},
.cp_seti = (struct hdmi_pll_cfg[]){
{34440000, 0x3F},
{36830000, 0x2F},
{68870000, 0x3F},
{73660000, 0x2F},
{137730000, 0x3F},
{147310000, 0x2F},
{275450000, 0x3F},
{294620000, 0x2F},
{344650000, 0x3F},
{363800000, 0x2F},
{477960000, 0x3F},
{512530000, 0x2F},
{550890000, 0x1F},
{589240000, 0x2F},
{630900000, 0x3F},
{650590000, 0x2F},
{689290000, 0x1F},
{727600000, 0x2F},
{HDMI_PLL_TMDS_MAX, 0x3F},
},
.ip_setp = (struct hdmi_pll_cfg[]){
{497340000, 0x03},
{512530000, 0x07},
{535680000, 0x03},
{550890000, 0x07},
{574060000, 0x03},
{727600000, 0x07},
{HDMI_PLL_TMDS_MAX, 0x03},
},
.cp_setp = (struct hdmi_pll_cfg[]){
{36830000, 0x1F},
{40010000, 0x17},
{73660000, 0x1F},
{80000000, 0x17},
{147310000, 0x1F},
{160010000, 0x17},
{294620000, 0x1F},
{363800000, 0x17},
{497340000, 0x0F},
{512530000, 0x1F},
{535680000, 0x0F},
{550890000, 0x1F},
{574060000, 0x0F},
{589240000, 0x1F},
{727600000, 0x17},
{HDMI_PLL_TMDS_MAX, 0x07},
},
.crctrl = (struct hdmi_pll_cfg[]){
{40010000, 0xBB},
{40030000, 0x77},
{80000000, 0xBB},
{80060000, 0x77},
{160010000, 0xBB},
{160120000, 0x77},
{772930000, 0xBB},
{HDMI_PLL_TMDS_MAX, 0xFF},
},
.c = {
.dbg_name = "hdmi_20nm_vco_clk",
.ops = &hdmi_20nm_vco_clk_ops,
CLK_INIT(hdmi_20nm_vco_clk.c),
},
};
static struct clk_lookup hdmipllcc_8994[] = {
CLK_LIST(hdmi_20nm_vco_clk),
};
int hdmi_20nm_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc = -ENOTSUPP;
if (!pll_res || !pll_res->phy_base || !pll_res->pll_base) {
pr_err("Invalide input parameters\n");
return -EPROBE_DEFER;
}
/* Set client data for vco, mux and div clocks */
hdmi_20nm_vco_clk.priv = pll_res;
rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_8994,
ARRAY_SIZE(hdmipllcc_8994));
if (rc) {
pr_err("Clock register failed rc=%d\n", rc);
rc = -EPROBE_DEFER;
} else {
pr_debug("%s: SUCCESS\n", __func__);
}
return rc;
}

1104
drivers/clk/msm/mdss/mdss-hdmi-pll-28hpm.c
View file

File diff suppressed because it is too large Load diff

84
drivers/clk/msm/mdss/mdss-pll.c
View file

@ -22,7 +22,6 @@
#include <linux/clk/msm-clock-generic.h>
#include "mdss-pll.h"
#include "mdss-edp-pll.h"
#include "mdss-dsi-pll.h"
#include "mdss-hdmi-pll.h"
@ -127,35 +126,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
goto err;
}
if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8916")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
pll_res->target_id = MDSS_PLL_TARGET_8916;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8939")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
pll_res->target_id = MDSS_PLL_TARGET_8939;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8909")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
pll_res->target_id = MDSS_PLL_TARGET_8909;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8974")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_HPM;
pll_res->target_id = MDSS_PLL_TARGET_8974;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8994")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;
pll_res->target_id = MDSS_PLL_TARGET_8994;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8992")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;
pll_res->target_id = MDSS_PLL_TARGET_8992;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996")) {
if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8996")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
pll_res->target_id = MDSS_PLL_TARGET_8996;
} else if (!strcmp(compatible_stream, "qcom,mdss_edp_pll")) {
pll_res->pll_interface_type = MDSS_EDP_PLL;
} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) {
pll_res->pll_interface_type = MDSS_HDMI_PLL;
} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8994")) {
pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8992")) {
pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) {
pll_res->pll_interface_type = MDSS_HDMI_PLL_8996;
} else {
@ -181,26 +154,9 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
}
switch (pll_res->pll_interface_type) {
case MDSS_DSI_PLL_LPM:
rc = dsi_pll_clock_register_lpm(pdev, pll_res);
break;
case MDSS_DSI_PLL_HPM:
rc = dsi_pll_clock_register_hpm(pdev, pll_res);
break;
case MDSS_DSI_PLL_20NM:
rc = dsi_pll_clock_register_20nm(pdev, pll_res);
break;
case MDSS_DSI_PLL_8996:
rc = dsi_pll_clock_register_8996(pdev, pll_res);
break;
case MDSS_EDP_PLL:
rc = edp_pll_clock_register(pdev, pll_res);
break;
case MDSS_HDMI_PLL:
rc = hdmi_pll_clock_register(pdev, pll_res);
case MDSS_HDMI_PLL_20NM:
rc = hdmi_20nm_pll_clock_register(pdev, pll_res);
break;
case MDSS_HDMI_PLL_8996:
rc = hdmi_8996_pll_clock_register(pdev, pll_res);
break;
@ -279,35 +235,9 @@ static int mdss_pll_probe(struct platform_device *pdev)
goto res_parse_error;
}
/*
* DSI PLL 1 is leaking current whenever MDSS GDSC is toggled. Need to
* map PLL1 registers along with the PLl0 so that we can manually turn
* off PLL1.
*/
if (pll_res->pll_interface_type == MDSS_DSI_PLL_20NM) {
struct resource *pll_1_base_reg;
pll_1_base_reg = platform_get_resource_byname(pdev,
IORESOURCE_MEM, "pll_1_base");
if (pll_1_base_reg) {
pll_res->pll_1_base = ioremap(pll_1_base_reg->start,
resource_size(pll_1_base_reg));
if (!pll_res->pll_1_base)
pr_err("Unable to remap pll 1 base resources\n");
} else {
pr_err("Unable to get the pll 1 base resource\n");
}
}
phy_base_reg = platform_get_resource_byname(pdev,
IORESOURCE_MEM, "phy_base");
if (!phy_base_reg) {
/* This resource is mandatory for HDMI pll */
if (pll_res->pll_interface_type == MDSS_HDMI_PLL) {
pr_err("Unable to get the phy base resources\n");
rc = -ENOMEM;
goto phy_io_error;
}
} else {
if (phy_base_reg) {
pll_res->phy_base = ioremap(phy_base_reg->start,
resource_size(phy_base_reg));
if (!pll_res->phy_base) {
@ -403,18 +333,8 @@ static int mdss_pll_remove(struct platform_device *pdev)
}
static const struct of_device_id mdss_pll_dt_match[] = {
{.compatible = "qcom,mdss_dsi_pll_8974"},
{.compatible = "qcom,mdss_dsi_pll_8994"},
{.compatible = "qcom,mdss_dsi_pll_8996"},
{.compatible = "qcom,mdss_hdmi_pll_8994"},
{.compatible = "qcom,mdss_dsi_pll_8992"},
{.compatible = "qcom,mdss_hdmi_pll_8992"},
{.compatible = "qcom,mdss_hdmi_pll_8996"},
{.compatible = "qcom,mdss_dsi_pll_8916"},
{.compatible = "qcom,mdss_dsi_pll_8939"},
{.compatible = "qcom,mdss_dsi_pll_8909"},
{.compatible = "qcom,mdss_edp_pll"},
{.compatible = "qcom,mdss_hdmi_pll"},
{}
};

12
drivers/clk/msm/mdss/mdss-pll.h
View file

@ -28,25 +28,13 @@
(base) + (offset))
enum {
MDSS_DSI_PLL_LPM,
MDSS_DSI_PLL_HPM,
MDSS_DSI_PLL_20NM,
MDSS_DSI_PLL_8996,
MDSS_EDP_PLL,
MDSS_HDMI_PLL,
MDSS_HDMI_PLL_20NM,
MDSS_HDMI_PLL_8996,
MDSS_UNKNOWN_PLL,
};
enum {
MDSS_PLL_TARGET_8974,
MDSS_PLL_TARGET_8994,
MDSS_PLL_TARGET_8992,
MDSS_PLL_TARGET_8996,
MDSS_PLL_TARGET_8916,
MDSS_PLL_TARGET_8939,
MDSS_PLL_TARGET_8909,
};
struct mdss_pll_resources {