Merge "ARM: dts: msm: Add CPU efficiency values for sdm630"
This commit is contained in:
commit
56c4888317
1 changed files with 4 additions and 4 deletions
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@ -48,7 +48,7 @@
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reg = <0x0 0x100>;
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reg = <0x0 0x100>;
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enable-method = "psci";
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile0>;
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qcom,limits-info = <&mitigation_profile0>;
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efficiency = <1024>;
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efficiency = <1126>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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compatible = "arm,arch-cache";
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@ -72,7 +72,7 @@
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reg = <0x0 0x101>;
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reg = <0x0 0x101>;
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enable-method = "psci";
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile1>;
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qcom,limits-info = <&mitigation_profile1>;
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efficiency = <1024>;
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efficiency = <1126>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&L2_1>;
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L1_I_101: l1-icache {
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L1_I_101: l1-icache {
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compatible = "arm,arch-cache";
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compatible = "arm,arch-cache";
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@ -90,7 +90,7 @@
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reg = <0x0 0x102>;
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reg = <0x0 0x102>;
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enable-method = "psci";
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile2>;
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qcom,limits-info = <&mitigation_profile2>;
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efficiency = <1024>;
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efficiency = <1126>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&L2_1>;
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L1_I_102: l1-icache {
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L1_I_102: l1-icache {
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compatible = "arm,arch-cache";
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compatible = "arm,arch-cache";
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@ -108,7 +108,7 @@
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reg = <0x0 0x103>;
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reg = <0x0 0x103>;
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enable-method = "psci";
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enable-method = "psci";
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qcom,limits-info = <&mitigation_profile3>;
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qcom,limits-info = <&mitigation_profile3>;
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efficiency = <1024>;
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efficiency = <1126>;
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next-level-cache = <&L2_1>;
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next-level-cache = <&L2_1>;
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L1_I_103: l1-icache {
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L1_I_103: l1-icache {
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compatible = "arm,arch-cache";
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compatible = "arm,arch-cache";
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