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ASoC: wcd9335: Reset spline resampler after playback

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Reset spline resampler after audio playback is completed
to clear the FIFO and avoid any noise being generated.

Change-Id: I30ed6a337c3bb08f6197f7ee575b323f0b0acfac
Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
This commit is contained in:
Phani Kumar Uppalapati 2016-01-08 16:16:03 -08:00 • committed by David Keitel
parent 905abbddb5
commit 58456af54d
1 changed files with 17 additions and 1 deletions
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18
sound/soc/codecs/wcd9335.c
View file

@ -4385,6 +4385,7 @@ static int tasha_codec_enable_spline_src(struct snd_soc_codec *codec,
int src_num, int src_num,
int event) int event)
{ {
u16 src_paired_reg;
struct tasha_priv *tasha; struct tasha_priv *tasha;
u16 rx_path_cfg_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; u16 rx_path_cfg_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
u16 rx_path_ctl_reg = WCD9335_CDC_RX1_RX_PATH_CTL; u16 rx_path_ctl_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
@ -4397,48 +4398,56 @@ static int tasha_codec_enable_spline_src(struct snd_soc_codec *codec,
case SRC_IN_HPHL: case SRC_IN_HPHL:
rx_path_cfg_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX1_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
spl_src = SPLINE_SRC0; spl_src = SPLINE_SRC0;
break; break;
case SRC_IN_LO1: case SRC_IN_LO1:
rx_path_cfg_reg = WCD9335_CDC_RX3_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX3_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX3_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
spl_src = SPLINE_SRC0; spl_src = SPLINE_SRC0;
break; break;
case SRC_IN_HPHR: case SRC_IN_HPHR:
rx_path_cfg_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX2_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
spl_src = SPLINE_SRC1; spl_src = SPLINE_SRC1;
break; break;
case SRC_IN_LO2: case SRC_IN_LO2:
rx_path_cfg_reg = WCD9335_CDC_RX4_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX4_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC1_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC0_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX4_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
spl_src = SPLINE_SRC1; spl_src = SPLINE_SRC1;
break; break;
case SRC_IN_SPKRL: case SRC_IN_SPKRL:
rx_path_cfg_reg = WCD9335_CDC_RX7_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX7_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX7_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
spl_src = SPLINE_SRC2; spl_src = SPLINE_SRC2;
break; break;
case SRC_IN_LO3: case SRC_IN_LO3:
rx_path_cfg_reg = WCD9335_CDC_RX5_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX5_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX5_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
spl_src = SPLINE_SRC2; spl_src = SPLINE_SRC2;
break; break;
case SRC_IN_SPKRR: case SRC_IN_SPKRR:
rx_path_cfg_reg = WCD9335_CDC_RX8_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX8_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX8_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
spl_src = SPLINE_SRC3; spl_src = SPLINE_SRC3;
break; break;
case SRC_IN_LO4: case SRC_IN_LO4:
rx_path_cfg_reg = WCD9335_CDC_RX6_RX_PATH_CFG0; rx_path_cfg_reg = WCD9335_CDC_RX6_RX_PATH_CFG0;
src_clk_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0; src_clk_reg = WCD9335_SPLINE_SRC3_CLK_RST_CTL_0;
src_paired_reg = WCD9335_SPLINE_SRC2_CLK_RST_CTL_0;
rx_path_ctl_reg = WCD9335_CDC_RX6_RX_PATH_CTL; rx_path_ctl_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
spl_src = SPLINE_SRC3; spl_src = SPLINE_SRC3;
break; break;
@ -4451,6 +4460,13 @@ static int tasha_codec_enable_spline_src(struct snd_soc_codec *codec,
count = *src_users; count = *src_users;
count++; count++;
if (count == 1) { if (count == 1) {
if ((snd_soc_read(codec, src_clk_reg) & 0x02) ||
(snd_soc_read(codec, src_paired_reg) & 0x02)) {
snd_soc_update_bits(codec, src_clk_reg, 0x02,
0x00);
snd_soc_update_bits(codec, src_paired_reg,
0x02, 0x00);
}
snd_soc_update_bits(codec, src_clk_reg, 0x01, 0x01); snd_soc_update_bits(codec, src_clk_reg, 0x01, 0x01);
snd_soc_update_bits(codec, rx_path_cfg_reg, 0x80, snd_soc_update_bits(codec, rx_path_cfg_reg, 0x80,
0x80); 0x80);
@ -4463,7 +4479,7 @@ static int tasha_codec_enable_spline_src(struct snd_soc_codec *codec,
if (count == 0) { if (count == 0) {
snd_soc_update_bits(codec, rx_path_cfg_reg, 0x80, snd_soc_update_bits(codec, rx_path_cfg_reg, 0x80,
0x00); 0x00);
snd_soc_update_bits(codec, src_clk_reg, 0x01, 0x00); snd_soc_update_bits(codec, src_clk_reg, 0x03, 0x02);
/* default sample rate */ /* default sample rate */
snd_soc_update_bits(codec, rx_path_ctl_reg, 0x0f, snd_soc_update_bits(codec, rx_path_ctl_reg, 0x0f,
0x04); 0x04);