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msm: mdss: update the DSI PHY regulator programming sequence

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For 28nm DSI PHY, update the regulator programming sequence
as per the system team's recommended settings.

Change-Id: I0bb23e0ee1e25994c4b9dd4cedd6cb46ea8e282c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
This commit is contained in:
Padmanabhan Komanduru 2014-10-28 23:12:48 +05:30 • committed by David Keitel
parent 4202f1aeae
commit 58cba6b3ca
1 changed files with 41 additions and 22 deletions
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63
drivers/video/fbdev/msm/msm_mdss_io_8974.c
View file

@ -149,29 +149,48 @@ static void mdss_dsi_28nm_phy_init(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
} }
} }
/* Regulator ctrl 0 */ if (pd->reg_ldo_mode) {
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x280, 0x0); /* Regulator ctrl 0 */
/* Regulator ctrl - CAL_PWR_CFG */ MIPI_OUTP((temp_ctrl->phy_io.base) + 0x280, 0x0);
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x298, pd->regulator[6]); /* Regulator ctrl - CAL_PWR_CFG */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x298, pd->regulator[6]);
/* Regulator ctrl - TEST */ /* Add H/w recommended delay */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x294, pd->regulator[5]); udelay(1000);
/* Regulator ctrl 3 */ /* Regulator ctrl - TEST */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x28c, pd->regulator[3]); MIPI_OUTP((temp_ctrl->phy_io.base) + 0x294, pd->regulator[5]);
/* Regulator ctrl 2 */ /* Regulator ctrl 3 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x288, pd->regulator[2]); MIPI_OUTP((temp_ctrl->phy_io.base) + 0x28c, pd->regulator[3]);
/* Regulator ctrl 1 */ /* Regulator ctrl 2 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x284, pd->regulator[1]); MIPI_OUTP((temp_ctrl->phy_io.base) + 0x288, pd->regulator[2]);
/* Regulator ctrl 0 */ /* Regulator ctrl 1 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x280, pd->regulator[0]); MIPI_OUTP((temp_ctrl->phy_io.base) + 0x284, pd->regulator[1]);
/* Regulator ctrl 4 */ /* Regulator ctrl 4 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x290, pd->regulator[4]); MIPI_OUTP((temp_ctrl->phy_io.base) + 0x290, pd->regulator[4]);
/* LDO ctrl */
/* LDO ctrl */ if (MIPI_INP(ctrl_pdata->ctrl_base) == MDSS_DSI_HW_REV_103_1)
if (pd->reg_ldo_mode) MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x05);
MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x25); else
else MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x0d);
} else {
/* Regulator ctrl 0 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x280, 0x0);
/* Regulator ctrl - CAL_PWR_CFG */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x298, pd->regulator[6]);
/* Add H/w recommended delay */
udelay(1000);
/* Regulator ctrl 1 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x284, pd->regulator[1]);
/* Regulator ctrl 2 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x288, pd->regulator[2]);
/* Regulator ctrl 3 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x28c, pd->regulator[3]);
/* Regulator ctrl 4 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x290, pd->regulator[4]);
/* LDO ctrl */
MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x00); MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x00);
/* Regulator ctrl 0 */
MIPI_OUTP((temp_ctrl->phy_io.base) + 0x280, pd->regulator[0]);
}
off = 0x0140; /* phy timing ctrl 0 - 11 */ off = 0x0140; /* phy timing ctrl 0 - 11 */
for (i = 0; i < 12; i++) { for (i = 0; i < 12; i++) {