rt2x00: Factor out TXWI writing to common rt2800 code.
TXWI writing is exactly the same for rt2800pci and rt2800usb, so make it common code. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gertjan van Wingerde
John W. Linville
parent
78b8f3b0dd
commit
59679b91d1
4 changed files with 60 additions and 102 deletions
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@ -281,6 +281,60 @@ int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
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}
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}
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EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
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EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
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void rt2800_write_txwi(struct sk_buff *skb, struct txentry_desc *txdesc)
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{
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__le32 *txwi = (__le32 *)(skb->data - TXWI_DESC_SIZE);
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u32 word;
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/*
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* Initialize TX Info descriptor
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*/
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rt2x00_desc_read(txwi, 0, &word);
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rt2x00_set_field32(&word, TXWI_W0_FRAG,
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test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
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rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
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rt2x00_set_field32(&word, TXWI_W0_TS,
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test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_AMPDU,
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test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
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rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
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rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
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rt2x00_set_field32(&word, TXWI_W0_BW,
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test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
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test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
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rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
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rt2x00_desc_write(txwi, 0, word);
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rt2x00_desc_read(txwi, 1, &word);
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rt2x00_set_field32(&word, TXWI_W1_ACK,
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test_bit(ENTRY_TXD_ACK, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W1_NSEQ,
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
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rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
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test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
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txdesc->key_idx : 0xff);
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rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
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txdesc->length);
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rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
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rt2x00_desc_write(txwi, 1, word);
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/*
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* Always write 0 to IV/EIV fields, hardware will insert the IV
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* from the IVEIV register when TXD_W3_WIV is set to 0.
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* When TXD_W3_WIV is set to 1 it will use the IV data
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* from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
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* crypto entry in the registers should be used to encrypt the frame.
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*/
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_rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
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_rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
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}
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EXPORT_SYMBOL_GPL(rt2800_write_txwi);
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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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const struct rt2x00debug rt2800_rt2x00debug = {
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const struct rt2x00debug rt2800_rt2x00debug = {
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.owner = THIS_MODULE,
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.owner = THIS_MODULE,
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@ -111,6 +111,8 @@ void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
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const u8 command, const u8 token,
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const u8 command, const u8 token,
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const u8 arg0, const u8 arg1);
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const u8 arg0, const u8 arg1);
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void rt2800_write_txwi(struct sk_buff *skb, struct txentry_desc *txdesc);
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extern const struct rt2x00debug rt2800_rt2x00debug;
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extern const struct rt2x00debug rt2800_rt2x00debug;
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int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev);
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int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev);
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@ -616,67 +616,13 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
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static int rt2800pci_write_tx_data(struct queue_entry* entry,
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static int rt2800pci_write_tx_data(struct queue_entry* entry,
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struct txentry_desc *txdesc)
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struct txentry_desc *txdesc)
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{
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{
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struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
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struct sk_buff *skb = entry->skb;
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struct skb_frame_desc *skbdesc;
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int ret;
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int ret;
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__le32 *txwi;
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u32 word;
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ret = rt2x00pci_write_tx_data(entry, txdesc);
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ret = rt2x00pci_write_tx_data(entry, txdesc);
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if (ret)
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if (ret)
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return ret;
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return ret;
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skbdesc = get_skb_frame_desc(skb);
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rt2800_write_txwi(entry->skb, txdesc);
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txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
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/*
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* Initialize TX Info descriptor
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*/
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rt2x00_desc_read(txwi, 0, &word);
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rt2x00_set_field32(&word, TXWI_W0_FRAG,
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test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
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rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
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rt2x00_set_field32(&word, TXWI_W0_TS,
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test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_AMPDU,
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test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
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rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
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rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
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rt2x00_set_field32(&word, TXWI_W0_BW,
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test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
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test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
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rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
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rt2x00_desc_write(txwi, 0, word);
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rt2x00_desc_read(txwi, 1, &word);
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rt2x00_set_field32(&word, TXWI_W1_ACK,
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test_bit(ENTRY_TXD_ACK, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W1_NSEQ,
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
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rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
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test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
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txdesc->key_idx : 0xff);
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rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
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txdesc->length);
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rt2x00_set_field32(&word, TXWI_W1_PACKETID,
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skbdesc->entry->queue->qid + 1);
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rt2x00_desc_write(txwi, 1, word);
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/*
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* Always write 0 to IV/EIV fields, hardware will insert the IV
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* from the IVEIV register when TXD_W3_WIV is set to 0.
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* When TXD_W3_WIV is set to 1 it will use the IV data
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* from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
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* crypto entry in the registers should be used to encrypt the frame.
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*/
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_rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
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_rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
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return 0;
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return 0;
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}
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}
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@ -401,59 +401,15 @@ static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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{
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{
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struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
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struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
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__le32 *txi = skbdesc->desc;
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__le32 *txi = skbdesc->desc;
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__le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
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u32 word;
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u32 word;
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/*
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/*
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* Initialize TX Info descriptor
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* Initialize TXWI descriptor
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*/
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*/
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rt2x00_desc_read(txwi, 0, &word);
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rt2800_write_txwi(skb, txdesc);
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rt2x00_set_field32(&word, TXWI_W0_FRAG,
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test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
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rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
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rt2x00_set_field32(&word, TXWI_W0_TS,
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test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_AMPDU,
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test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
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rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
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rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
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rt2x00_set_field32(&word, TXWI_W0_BW,
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test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
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test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
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rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
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rt2x00_desc_write(txwi, 0, word);
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rt2x00_desc_read(txwi, 1, &word);
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rt2x00_set_field32(&word, TXWI_W1_ACK,
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test_bit(ENTRY_TXD_ACK, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W1_NSEQ,
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test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
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rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
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rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
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test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
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txdesc->key_idx : 0xff);
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rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
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txdesc->length);
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rt2x00_set_field32(&word, TXWI_W1_PACKETID,
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skbdesc->entry->queue->qid + 1);
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rt2x00_desc_write(txwi, 1, word);
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/*
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/*
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* Always write 0 to IV/EIV fields, hardware will insert the IV
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* Initialize TXINFO descriptor
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* from the IVEIV register when TXINFO_W0_WIV is set to 0.
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* When TXINFO_W0_WIV is set to 1 it will use the IV data
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* from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
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* crypto entry in the registers should be used to encrypt the frame.
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*/
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_rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
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_rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
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/*
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* Initialize TX descriptor
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*/
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*/
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rt2x00_desc_read(txi, 0, &word);
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rt2x00_desc_read(txi, 0, &word);
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rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
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rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
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