drm/ast: Fix incorrect register check for DRAM width
commit 2d02b8bdba322b527c5f5168ce1ca10c2d982a78 upstream. During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -227,7 +227,7 @@ static int ast_get_dram_info(struct drm_device *dev)
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} while (ast_read32(ast, 0x10000) != 0x01);
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data = ast_read32(ast, 0x10004);
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if (data & 0x400)
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if (data & 0x40)
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ast->dram_bus_width = 16;
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else
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ast->dram_bus_width = 32;
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