evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

clk: mdss: write lane mode when powering on HDMI PHY

Browse source 
To improve the timing margin, lane mode selection
needs to be written during the HDMI PHY startup
sequence. This prevents a timing failure when
VDDCX or VCCA_CORE are applied rather than the
nominal value.

Change-Id: I2ed54f63903a473eca12fb4d8f3b542585397dae
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
This commit is contained in:
Casey Piper 2015-03-11 18:25:03 -07:00 • committed by David Keitel
parent 0b02573adc
commit 5a356b88c8
1 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c
View file

@ -762,6 +762,10 @@ static int hdmi_thulium_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
QSERDES_TX_L0_CLKBUF_ENABLE, 0x03);
MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET,
QSERDES_TX_L0_CLKBUF_ENABLE, 0x03);
MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,
QSERDES_TX_L0_LANE_MODE, 0x03);
MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET,
QSERDES_TX_L0_LANE_MODE, 0x03);
MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET,
QSERDES_TX_L0_TX_BAND, cfg.tx_l0_tx_band);