From b1213275c880e4017fe6db02594645ad53940767 Mon Sep 17 00:00:00 2001
From: Santosh Mardi <gsantosh@codeaurora.org>
Date: Sat, 31 Dec 2016 17:00:32 +0530
Subject: [PATCH] ARM: dts: msm: add cpufreq node for SDM660

Add cpufreq device node for SDM660 target which
helps cpu core frequency scaling.

Change-Id: Idca3fd5959ac83bfd9abaf929f4c6fc405a6bf10
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
---
 arch/arm/boot/dts/qcom/sdm660.dtsi | 38 ++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/sdm660.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi
index 856608e4e47a..2e97d9d3adc1 100644
--- a/arch/arm/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660.dtsi
@@ -18,6 +18,7 @@
 #include <dt-bindings/clock/audio-ext-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/clock/qcom,cpu-osm.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. SDM 660";
@@ -1178,6 +1179,43 @@
 		#clock-cells = <1>;
 	};
 
+	msm_cpufreq: qcom,msm-cpufreq {
+		compatible = "qcom,msm-cpufreq";
+		clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk",
+				"cpu3_clk", "cpu4_clk", "cpu5_clk",
+				"cpu6_clk", "cpu7_clk";
+		clocks = <&clock_cpu PWRCL_CLK>,
+			 <&clock_cpu PWRCL_CLK>,
+			 <&clock_cpu PWRCL_CLK>,
+			 <&clock_cpu PWRCL_CLK>,
+			 <&clock_cpu PERFCL_CLK>,
+			 <&clock_cpu PERFCL_CLK>,
+			 <&clock_cpu PERFCL_CLK>,
+			 <&clock_cpu PERFCL_CLK>;
+
+		qcom,governor-per-policy;
+
+		qcom,cpufreq-table-0 =
+			<  300000 >,
+			<  633600 >,
+			<  902400 >,
+			< 1113600 >,
+			< 1401600 >,
+			< 1536000 >,
+			< 1747200 >,
+			< 1843200 >;
+
+		qcom,cpufreq-table-4 =
+			<  300000 >,
+			< 1113600 >,
+			< 1401600 >,
+			< 1747200 >,
+			< 1958400 >,
+			< 2150400 >,
+			< 2208000 >,
+			< 2457600 >;
+	};
+
 	sdhc_1: sdhci@c0c4000 {
 		compatible = "qcom,sdhci-msm-v5";
 		reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;