drm/msm: Add timestamp counter
In the confusion of adding the perfcounter API the timestamp query was broken. Convert the query over to the perfcounter API to avoid confusion. Change-Id: Ic0dedbad590489a643e8aa6d678bf19f732c06dd Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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2 changed files with 10 additions and 2 deletions
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@ -774,6 +774,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
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gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
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gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
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gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
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a5xx_gpu->timestamp_counter = adreno_get_counter(gpu,
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MSM_COUNTER_GROUP_CP, 0, NULL, NULL);
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/* Load the GPMU firmware before starting the HW init */
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/* Load the GPMU firmware before starting the HW init */
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a5xx_gpmu_ucode_init(gpu);
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a5xx_gpmu_ucode_init(gpu);
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@ -1218,8 +1221,11 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
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static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
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static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
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{
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{
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*value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO,
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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REG_A5XX_RBBM_PERFCTR_CP_0_HI);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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*value = adreno_read_counter(gpu, MSM_COUNTER_GROUP_CP,
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a5xx_gpu->timestamp_counter);
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return 0;
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return 0;
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}
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}
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@ -56,6 +56,8 @@ struct a5xx_gpu {
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struct a5xx_smmu_info *smmu_info;
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struct a5xx_smmu_info *smmu_info;
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struct drm_gem_object *smmu_info_bo;
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struct drm_gem_object *smmu_info_bo;
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uint64_t smmu_info_iova;
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uint64_t smmu_info_iova;
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int timestamp_counter;
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};
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};
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#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)
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#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)
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