msm: pcie: update PCIe PHY DUMP sequence for mdmcalifornium
Update the PCIe PHY DUMP sequence for mdmcalifornium based on new settings while maintaining backward compatibility. Change-Id: I8711709dee73d9552c911d10a71e2081d789a51b Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong
David Keitel
parent
ed41926607
commit
5e06e809da
1 changed files with 167 additions and 134 deletions
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@ -1,4 +1,4 @@
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/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -56,6 +56,7 @@
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#define TX_BASE 0x200
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#define RX_BASE 0x400
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#define PCS_BASE 0x800
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#define PCS_MISC_BASE 0x600
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#else
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#define PCIE_VENDOR_ID_RCP 0x17cb
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#define PCIE_DEVICE_ID_RCP 0x0104
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@ -66,11 +67,13 @@
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#define TX_BASE 0x1000
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#define RX_BASE 0x1200
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#define PCS_BASE 0x1400
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#define PCS_MISC_BASE 0
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#endif
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#define TX(n, m) (TX_BASE + n * m * 0x1000)
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#define RX(n, m) (RX_BASE + n * m * 0x1000)
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#define PCS_PORT(n, m) (PCS_BASE + n * m * 0x1000)
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#define PCS_MISC_PORT(n, m) (PCS_MISC_BASE + n * m * 0x1000)
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#define QSERDES_COM_BG_TIMER 0x00C
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#define QSERDES_COM_SSC_EN_CENTER 0x010
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@ -141,6 +144,15 @@
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#define QSERDES_RX_N_SIGDET_LVL(n, m) (RX(n, m) + 0x118)
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#define QSERDES_RX_N_RX_BAND(n, m) (RX(n, m) + 0x120)
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#define PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x00)
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#define PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x04)
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#define PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x08)
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#define PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x0C)
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#define PCIE_MISC_N_DEBUG_BUS_0_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x14)
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#define PCIE_MISC_N_DEBUG_BUS_1_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x18)
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#define PCIE_MISC_N_DEBUG_BUS_2_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x1C)
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#define PCIE_MISC_N_DEBUG_BUS_3_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x20)
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#define PCIE_N_SW_RESET(n, m) (PCS_PORT(n, m) + 0x00)
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#define PCIE_N_POWER_DOWN_CONTROL(n, m) (PCS_PORT(n, m) + 0x04)
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#define PCIE_N_START_CONTROL(n, m) (PCS_PORT(n, m) + 0x08)
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@ -939,6 +951,61 @@ static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
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return true;
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}
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#else
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static void pcie_phy_dump_test_cntrl(struct msm_pcie_dev_t *dev,
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u32 cntrl4_val, u32 cntrl5_val,
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u32 cntrl6_val, u32 cntrl7_val)
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{
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy), cntrl4_val);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy), cntrl5_val);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy), cntrl6_val);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy), cntrl7_val);
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL4(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL5(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL6(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL7(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_0_STATUS: 0x%x\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n", dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx,
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dev->common_phy)));
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}
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static void pcie_phy_dump(struct msm_pcie_dev_t *dev)
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{
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int i, size;
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@ -946,75 +1013,109 @@ static void pcie_phy_dump(struct msm_pcie_dev_t *dev)
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PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx);
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for (i = 0; i < 12; i += 4) {
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write_val = 0x18 + i;
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy),
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write_val);
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pcie_phy_dump_test_cntrl(dev, 0x18, 0x19, 0x1A, 0x1B);
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pcie_phy_dump_test_cntrl(dev, 0x1C, 0x1D, 0x1E, 0x1F);
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pcie_phy_dump_test_cntrl(dev, 0x20, 0x21, 0x22, 0x23);
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write_val++;
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for (i = 0; i < 3; i++) {
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write_val = 0x1 + i;
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy),
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write_val);
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QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
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dev->common_phy), write_val);
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PCIE_DUMP(dev,
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"PCIe: RC%d QSERDES_TX_N_DEBUG_BUS_SEL: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
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dev->common_phy)));
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pcie_phy_dump_test_cntrl(dev, 0x30, 0x31, 0x32, 0x33);
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}
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pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0);
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if (dev->phy_ver >= 0x10 && dev->phy_ver < 0x20) {
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pcie_phy_dump_test_cntrl(dev, 0x01, 0x02, 0x03, 0x0A);
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pcie_phy_dump_test_cntrl(dev, 0x0E, 0x0F, 0x12, 0x13);
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pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0);
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for (i = 0; i < 8; i += 4) {
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write_val = 0x1 + i;
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msm_pcie_write_reg(dev->phy,
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PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(dev->rc_idx,
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dev->common_phy), write_val);
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msm_pcie_write_reg(dev->phy,
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PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(dev->rc_idx,
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dev->common_phy), write_val + 1);
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msm_pcie_write_reg(dev->phy,
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PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(dev->rc_idx,
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dev->common_phy), write_val + 2);
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msm_pcie_write_reg(dev->phy,
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PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(dev->rc_idx,
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dev->common_phy), write_val + 3);
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PCIE_DUMP(dev,
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"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(
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dev->rc_idx, dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(
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dev->rc_idx, dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(
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dev->rc_idx, dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(
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dev->rc_idx, dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_0_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_0_STATUS(
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dev->rc_idx, dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_1_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_1_STATUS(
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dev->rc_idx, dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_2_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_2_STATUS(
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dev->rc_idx, dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_3_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_MISC_N_DEBUG_BUS_3_STATUS(
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dev->rc_idx, dev->common_phy)));
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}
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write_val++;
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy),
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write_val);
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write_val++;
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PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(
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dev->rc_idx, dev->common_phy), 0);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy),
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write_val);
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL4(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL5(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL6(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL7(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_PHY_DEBUG_BUS_0_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(
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dev->rc_idx, dev->common_phy), 0);
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msm_pcie_write_reg(dev->phy,
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PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(
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dev->rc_idx, dev->common_phy), 0);
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msm_pcie_write_reg(dev->phy,
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PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(
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dev->rc_idx, dev->common_phy), 0);
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}
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for (i = 0; i < 2; i++) {
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@ -1045,75 +1146,7 @@ static void pcie_phy_dump(struct msm_pcie_dev_t *dev)
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readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS3));
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}
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for (i = 0; i < 3; i++) {
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write_val = 0x1 + i;
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msm_pcie_write_reg(dev->phy,
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QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
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dev->common_phy),
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write_val);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy),
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0x30);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy),
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0x31);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy),
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0x32);
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msm_pcie_write_reg(dev->phy,
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PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy),
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0x33);
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL4(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL5(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL6(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_TEST_CONTROL7(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_PHY_DEBUG_BUS_0_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx,
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dev->common_phy)));
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PCIE_DUMP(dev,
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"PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n",
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dev->rc_idx,
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readl_relaxed(dev->phy +
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PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx,
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||||
dev->common_phy)));
|
||||
}
|
||||
msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL, 0);
|
||||
|
||||
if (dev->common_phy) {
|
||||
msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue