evie/android_kernel_oneplus_msm8998
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clk: qcom: Remove BRANCH_HALT_NO_CHECK_ON_DISABLE flag

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Remove BRANCH_HALT_NO_CHECK_ON_DISABLE flag for the clocks
with no branch halt status check during clock disable as
same functionality can be obtained with BRANCH_VOTED flag
so replacing the existing flag with BRANCH_VOTED flag.

Change-Id: I17935e4aa6144e3825e6922d95f671f9cecc0fe3
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
This commit is contained in:
Amit Nischal 2016-10-21 21:08:02 +05:30
parent fd45ca9c59
commit 5f559180ab
2 changed files with 11 additions and 11 deletions
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10
drivers/clk/qcom/gcc-msm8996.c
View file

@ -1253,7 +1253,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
static struct clk_branch gcc_mmss_bimc_gfx_clk = { static struct clk_branch gcc_mmss_bimc_gfx_clk = {
.halt_reg = 0x9010, .halt_reg = 0x9010,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x9010, .enable_reg = 0x9010,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2692,7 +2692,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
static struct clk_branch gcc_smmu_aggre0_axi_clk = { static struct clk_branch gcc_smmu_aggre0_axi_clk = {
.halt_reg = 0x81014, .halt_reg = 0x81014,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x81014, .enable_reg = 0x81014,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2717,7 +2717,7 @@ static struct clk_gate2 gcc_aggre0_noc_qosgen_extref_clk = {
static struct clk_branch gcc_smmu_aggre0_ahb_clk = { static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
.halt_reg = 0x81018, .halt_reg = 0x81018,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x81018, .enable_reg = 0x81018,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2871,7 +2871,7 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
static struct clk_branch hlos1_vote_lpass_core_smmu_clk = { static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {
.halt_reg = 0x7d010, .halt_reg = 0x7d010,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x7d010, .enable_reg = 0x7d010,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2884,7 +2884,7 @@ static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {
static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
.halt_reg = 0x7d014, .halt_reg = 0x7d014,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x7d014, .enable_reg = 0x7d014,
.enable_mask = BIT(0), .enable_mask = BIT(0),

12
drivers/clk/qcom/gcc-msmfalcon.c
View file

@ -1173,7 +1173,7 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
static struct clk_branch gcc_bimc_gfx_clk = { static struct clk_branch gcc_bimc_gfx_clk = {
.halt_reg = 0x7106c, .halt_reg = 0x7106c,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x7106c, .enable_reg = 0x7106c,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -1711,7 +1711,7 @@ static struct clk_branch gcc_gp3_clk = {
static struct clk_branch gcc_gpu_bimc_gfx_clk = { static struct clk_branch gcc_gpu_bimc_gfx_clk = {
.halt_reg = 0x71010, .halt_reg = 0x71010,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x71010, .enable_reg = 0x71010,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -1737,7 +1737,7 @@ static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
static struct clk_branch gcc_gpu_cfg_ahb_clk = { static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004, .halt_reg = 0x71004,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x71004, .enable_reg = 0x71004,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2516,7 +2516,7 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
.halt_reg = 0x7d014, .halt_reg = 0x7d014,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x7d014, .enable_reg = 0x7d014,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2529,7 +2529,7 @@ static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = { static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = {
.halt_reg = 0x7d048, .halt_reg = 0x7d048,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x7d048, .enable_reg = 0x7d048,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2542,7 +2542,7 @@ static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = {
static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = { static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = {
.halt_reg = 0x7e048, .halt_reg = 0x7e048,
.halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, .halt_check = BRANCH_VOTED,
.clkr = { .clkr = {
.enable_reg = 0x7e048, .enable_reg = 0x7e048,
.enable_mask = BIT(0), .enable_mask = BIT(0),