msm: mdss: Fix ctl flush bits reset by dspp programming
If MDP fence timeout happens, then to handle it gracefully we stage border fill. In this regard as the mixer config has now changed, then ctl flush has to be set. Starting for Ia510fc6377c5b328cb4225a4725275d86b72dbff, ctl flush bits were getting reset. Fix this in case mixer is setup again with borderfill. Change-Id: I12f60472e8f0f5630e239fb4b4026fda0d2f7cba Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org> Signed-off-by: Harsh Sahu <hsahu@codeaurora.org>
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1 changed files with 2 additions and 2 deletions
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@ -5834,10 +5834,10 @@ int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg,
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sctl->flush_bits = 0;
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sctl_flush_bits = 0;
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} else {
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sctl_flush_bits = sctl->flush_bits;
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sctl_flush_bits |= sctl->flush_bits;
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}
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}
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ctl_flush_bits = ctl->flush_bits;
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ctl_flush_bits |= ctl->flush_bits;
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mutex_unlock(&ctl->flush_lock);
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}
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/*
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