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ARM: dts: msm: add etm save restore nodes for sdm630

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Values stored in etm are lost across power collapse.
Add etm save retore nodes which saves etm
values across power collapse.

Change-Id: I9ceb89a255847ca1d9dc01f223283f5664cb8feb
CRs-fixed: 1112224
Signed-off-by: Amey Telawane <ameyt@codeaurora.org>
This commit is contained in:
Amey Telawane 2017-01-17 11:23:08 +05:30
parent 4331c08bf9
commit 636c58c3b6
1 changed files with 103 additions and 0 deletions
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103
arch/arm/boot/dts/qcom/sdm630.dtsi
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@ -671,6 +671,7 @@
qcom,pet-time = <10000>;
qcom,ipi-ping;
qcom,wakeup-enable;
qcom,scandump-size = <0x40000>;
};
uartblsp1dm1: serial@0c170000 {
@ -1378,6 +1379,108 @@
0x178a80b8 0x178b80b8>;
};
jtag_fuse: jtagfuse@786040 {
compatible = "qcom,jtag-fuse-v4";
reg = <0x786040 0x8>;
reg-names = "fuse-base";
};
jtag_mm0: jtagmm@7840000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7840000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm1: jtagmm@7940000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7940000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm2: jtagmm@7a40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7a40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm3: jtagmm@7b40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7b40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
jtag_mm4: jtagmm@7c40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7c40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm5: jtagmm@7d40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7d40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm6: jtagmm@7e40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7e40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm7: jtagmm@7f40000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7f40000 0x1000>;
reg-names = "etm-base";
clocks = <&clock_rpmcc RPM_QDSS_CLK>,
<&clock_rpmcc RPM_QDSS_A_CLK>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
spmi_bus: qcom,spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x800f000 0x1000>,