evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

pinctrl: qcom: msmfalcon: Update gpios as per latest gpio map

Browse source 
UART and SPI gpios are changed as per latest hardware definitions,
so updating them.

Change-Id: I0e06be169edc2eb1d35ef7fc6c41ff1809aebd03
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
This commit is contained in:
Venkatesh Yadav Abbarapu 2016-11-15 11:28:43 +05:30
parent 61f26e3aa5
commit 640d5e9d1d
1 changed files with 16 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

31
drivers/pinctrl/qcom/pinctrl-msmfalcon.c
View file

@ -748,10 +748,10 @@ static const char * const blsp_i2c5_groups[] = {
"gpio18", "gpio19",
};
static const char * const blsp_spi6_groups[] = {
"gpio20", "gpio21", "gpio22", "gpio23",
"gpio49", "gpio52", "gpio22", "gpio23",
};
static const char * const blsp_uart2_groups[] = {
"gpio20", "gpio21", "gpio22", "gpio23",
"gpio4", "gpio5", "gpio6", "gpio7",
};
static const char * const blsp_uim6_groups[] = {
"gpio20", "gpio21",
@ -1495,13 +1495,14 @@ static const struct msm_pingroup msmfalcon_groups[] = {
NA, NA),
PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, NA, NA,
atest_tsens2, atest_usb1, NA),
PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, NA, phase_flag3, NA, NA, NA,
PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag3, NA,
NA, NA, NA, NA),
PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag14, NA,
NA, NA, NA, NA),
PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, phase_flag31, NA,
NA, NA, NA, NA),
PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, NA, NA, NA, NA,
NA, NA),
PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, NA, phase_flag14, NA, NA, NA,
NA, NA),
PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, NA, phase_flag31, NA, NA, NA,
NA, NA),
PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(8, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc1,
atest_usb13, bimc_dte1, NA),
PINGROUP(9, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc0,
@ -1526,13 +1527,13 @@ static const struct msm_pingroup msmfalcon_groups[] = {
NA, NA),
PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA,
NA, NA),
PINGROUP(20, SOUTH, blsp_spi6, blsp_uart2, blsp_uim6, NA, NA, NA, NA,
PINGROUP(20, SOUTH, NA, NA, blsp_uim6, NA, NA, NA, NA,
NA, NA),
PINGROUP(21, SOUTH, blsp_spi6, blsp_uart2, blsp_uim6, NA, phase_flag11,
PINGROUP(21, SOUTH, NA, NA, blsp_uim6, NA, phase_flag11,
qdss_cti0_b, vsense_data0, NA, NA),
PINGROUP(22, CENTER, blsp_spi6, blsp_uart2, blsp_i2c6, NA,
PINGROUP(22, CENTER, blsp_spi6, NA, blsp_i2c6, NA,
phase_flag12, vsense_data1, NA, NA, NA),
PINGROUP(23, CENTER, blsp_spi6, blsp_uart2, blsp_i2c6, NA,
PINGROUP(23, CENTER, blsp_spi6, NA, blsp_i2c6, NA,
phase_flag13, vsense_mode, NA, NA, NA),
PINGROUP(24, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_clk, NA,
NA, phase_flag17, vsense_clkout, NA),
@ -1580,13 +1581,13 @@ static const struct msm_pingroup msmfalcon_groups[] = {
NA, NA, NA),
PINGROUP(48, SOUTH, NA, phase_flag1, qdss_gpio15, NA, NA, NA, NA, NA,
NA),
PINGROUP(49, SOUTH, NA, phase_flag2, qdss_cti0_a, NA, NA, NA, NA, NA,
NA),
PINGROUP(49, SOUTH, blsp_spi6, phase_flag2, qdss_cti0_a, NA, NA, NA,
NA, NA, NA),
PINGROUP(50, SOUTH, qspi_cs, NA, phase_flag9, qdss_cti0_a, NA, NA, NA,
NA, NA),
PINGROUP(51, SOUTH, qspi_data3, NA, phase_flag15, qdss_gpio8, NA, NA,
NA, NA, NA),
PINGROUP(52, SOUTH, CCI_TIMER2, blsp_spi8_b, blsp_i2c8_b, NA,
PINGROUP(52, SOUTH, CCI_TIMER2, blsp_spi8_b, blsp_i2c8_b, blsp_spi6,
phase_flag16, qdss_gpio, NA, NA, NA),
PINGROUP(53, NORTH, NA, phase_flag6, qdss_cti1_a, NA, NA, NA, NA, NA,
NA),