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ath9k: Initialize pll_pwrsave for AR9462/AR9565

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Cards based on AR9462/AR9565 support more PCIE
power save mechanisms, so register them correctly.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Sujith Manoharan 2015-03-09 14:20:08 +05:30 • committed by Kalle Valo
parent afa7e6dbd9
commit 656cd75c38
3 changed files with 5 additions and 1 deletions
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3
drivers/net/wireless/ath/ath9k/hw.c
View file

@ -366,6 +366,9 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
ah->config.rimt_first = 700; ah->config.rimt_first = 700;
} }
if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
ah->config.pll_pwrsave = 7;
/* /*
* We need this for PCI devices only (Cardbus, PCI, miniPCI) * We need this for PCI devices only (Cardbus, PCI, miniPCI)
* _and_ if on non-uniprocessor systems (Multiprocessor/HT). * _and_ if on non-uniprocessor systems (Multiprocessor/HT).

2
drivers/net/wireless/ath/ath9k/hw.h
View file

@ -341,7 +341,7 @@ struct ath9k_ops_config {
u32 ant_ctrl_comm2g_switch_enable; u32 ant_ctrl_comm2g_switch_enable;
bool xatten_margin_cfg; bool xatten_margin_cfg;
bool alt_mingainidx; bool alt_mingainidx;
bool pll_pwrsave; u8 pll_pwrsave;
bool tx_gain_buffalo; bool tx_gain_buffalo;
bool led_active_high; bool led_active_high;
}; };

1
drivers/net/wireless/ath/ath9k/init.c
View file

@ -440,6 +440,7 @@ static void ath9k_init_pcoem_platform(struct ath_softc *sc)
/* /*
* The default value of pll_pwrsave is 1. * The default value of pll_pwrsave is 1.
* For certain AR9485 cards, it is set to 0. * For certain AR9485 cards, it is set to 0.
* For AR9462, AR9565 it's set to 7.
*/ */
ah->config.pll_pwrsave = 1; ah->config.pll_pwrsave = 1;