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ARM: dts: msm: Add thermal mitigation properties to msmtriton

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Add thermal properties to enable kernel thermal monitoring and
mitigations like hotplug, thermal reset, vdd restriction, etc.
for msmtriton. Add mitigation profiles for each physical CPU which
has information like sensor to monitor and various mitigation types
to enable for msmtriton.

Change-Id: Ie85f7ede2d91767d0d5d20c90a481e6365ad7189
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
This commit is contained in:
Manaf Meethalavalappu Pallikunhi 2016-12-15 12:48:37 +05:30
parent f826f7e32a
commit 65f2f71b1f
1 changed files with 74 additions and 0 deletions
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74
arch/arm/boot/dts/qcom/msmtriton.dtsi
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@ -46,6 +46,7 @@
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile0>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
@ -69,6 +70,7 @@
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile1>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
@ -86,6 +88,7 @@
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile2>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
@ -103,6 +106,7 @@
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile3>;
efficiency = <1024>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
@ -120,6 +124,7 @@
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
@ -143,6 +148,7 @@
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
@ -160,6 +166,7 @@
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
@ -177,6 +184,7 @@
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
qcom,limits-info = <&mitigation_profile4>;
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
@ -547,6 +555,72 @@
};
};
mitigation_profile0: qcom,limit_info-0 {
qcom,temperature-sensor = <&sensor_information3>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile1: qcom,limit_info-1 {
qcom,temperature-sensor = <&sensor_information4>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile2: qcom,limit_info-2 {
qcom,temperature-sensor = <&sensor_information5>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile3: qcom,limit_info-3 {
qcom,temperature-sensor = <&sensor_information6>;
qcom,hotplug-mitigation-enable;
};
mitigation_profile4: qcom,limit_info-4 {
qcom,temperature-sensor = <&sensor_information1>;
qcom,hotplug-mitigation-enable;
};
qcom,msm-thermal {
compatible = "qcom,msm-thermal";
qcom,sensor-id = <3>;
qcom,poll-ms = <100>;
qcom,therm-reset-temp = <115>;
qcom,core-limit-temp = <70>;
qcom,core-temp-hysteresis = <10>;
qcom,hotplug-temp = <105>;
qcom,hotplug-temp-hysteresis = <20>;
qcom,online-hotplug-core;
qcom,synchronous-cluster-id = <0 1>;
qcom,synchronous-cluster-map = <0 4 &CPU4 &CPU5 &CPU6 &CPU7>,
<1 4 &CPU0 &CPU1 &CPU2 &CPU3>;
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
vdd-dig-supply = <&pm2falcon_s3_floor_level>;
vdd-gfx-supply = <&gfx_vreg_corner>;
qcom,vdd-dig-rstr{
qcom,vdd-rstr-reg = "vdd-dig";
qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM
RPM_SMD_REGULATOR_LEVEL_TURBO
RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_NONE>;
};
qcom,vdd-gfx-rstr{
qcom,vdd-rstr-reg = "vdd-gfx";
qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */
qcom,min-level = <1>; /* No Request */
};
msm_thermal_freq: qcom,vdd-apps-rstr{
qcom,vdd-rstr-reg = "vdd-apps";
qcom,levels = <1248000>;
qcom,freq-req;
};
};
wdog: qcom,wdt@17817000 {
status = "disabled";
compatible = "qcom,msm-watchdog";