ARM: dts: msm: Support AVS_CTL register write for msmcobalt
CPRh communicates voltages to the PMIC via L2 SAW4. APCLUS{0,1}_L2_SAW4_AVS_CTL/LIMIT registers need to be programmed for CPRh operation. CRs-fixed: 987593 Change-Id: I635d710759a94e2bb29fd3c7811816d09243de50 Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
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@ -11,6 +11,38 @@
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*/
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&soc {
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qcom,spm@178120000 {
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compatible = "qcom,spm-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x17812000 0x1000>;
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qcom,name = "gold-l2"; /* Gold L2 SAW */
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qcom,saw2-ver-reg = <0xfd0>;
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qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
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qcom,vctl-timeout-us = <50>;
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qcom,vctl-port = <0x0>;
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qcom,phase-port = <0x1>;
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qcom,saw2-avs-ctl = <0x1010031>;
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qcom,saw2-avs-limit = <0x4000208>;
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qcom,pfm-port = <0x2>;
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};
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qcom,spm@179120000 {
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compatible = "qcom,spm-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x17912000 0x1000>;
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qcom,name = "silver-l2"; /* Silver L2 SAW */
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qcom,saw2-ver-reg = <0xfd0>;
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qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
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qcom,vctl-timeout-us = <50>;
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qcom,vctl-port = <0x0>;
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qcom,phase-port = <0x1>;
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qcom,saw2-avs-ctl = <0x1010031>;
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qcom,saw2-avs-limit = <0x4000208>;
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qcom,pfm-port = <0x2>;
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};
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qcom,lpm-levels {
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compatible = "qcom,lpm-levels";
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qcom,use-psci;
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