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ARM: dts: msm: Support AVS_CTL register write for msmcobalt

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CPRh communicates voltages to the PMIC via L2 SAW4.
APCLUS{0,1}_L2_SAW4_AVS_CTL/LIMIT registers need to be programmed for
CPRh operation.

CRs-fixed: 987593
Change-Id: I635d710759a94e2bb29fd3c7811816d09243de50
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
This commit is contained in:
Archana Sathyakumar 2016-03-25 15:36:47 -06:00 • committed by Jeevan Shriram
parent dde29b75eb
commit 668a772675
1 changed files with 32 additions and 0 deletions
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32
arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi
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@ -11,6 +11,38 @@
*/
&soc {
qcom,spm@178120000 {
compatible = "qcom,spm-v2";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x17812000 0x1000>;
qcom,name = "gold-l2"; /* Gold L2 SAW */
qcom,saw2-ver-reg = <0xfd0>;
qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,vctl-timeout-us = <50>;
qcom,vctl-port = <0x0>;
qcom,phase-port = <0x1>;
qcom,saw2-avs-ctl = <0x1010031>;
qcom,saw2-avs-limit = <0x4000208>;
qcom,pfm-port = <0x2>;
};
qcom,spm@179120000 {
compatible = "qcom,spm-v2";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x17912000 0x1000>;
qcom,name = "silver-l2"; /* Silver L2 SAW */
qcom,saw2-ver-reg = <0xfd0>;
qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,vctl-timeout-us = <50>;
qcom,vctl-port = <0x0>;
qcom,phase-port = <0x1>;
qcom,saw2-avs-ctl = <0x1010031>;
qcom,saw2-avs-limit = <0x4000208>;
qcom,pfm-port = <0x2>;
};
qcom,lpm-levels {
compatible = "qcom,lpm-levels";
qcom,use-psci;