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ARM: dts: msm: Enable lpass dts over virtual platform

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add device node needed for lpass, adsp loader

CRs-Fixed: 2085351
Change-Id: I7d2b21625e92af4fb4a190942d27037c1f6afd67
Signed-off-by: Yonghui Zhang <yonghuiz@codeaurora.org>
This commit is contained in:
Yonghui Zhang 2017-07-31 13:49:17 +08:00 • committed by Gerrit - the friendly Code Review server
parent 1ec7c4119f
commit 66a0a667f4
1 changed files with 41 additions and 0 deletions
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41
arch/arm/boot/dts/qcom/vplatform-lfv-msm8996.dts
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@ -65,6 +65,11 @@
no-map; no-map;
reg = <0 0x88800000 0 0x6200000>; reg = <0 0x88800000 0 0x6200000>;
}; };
peripheral_mem: peripheral_region@8ea00000 {
compatible = "removed-dma-pool";
no-map;
reg = <0 0x8ea00000 0 0x2b00000>;
};
}; };
}; };
@ -131,6 +136,11 @@
asoc-codec = <&stub_codec>; asoc-codec = <&stub_codec>;
asoc-codec-names = "msm-stub-codec.1"; asoc-codec-names = "msm-stub-codec.1";
}; };
qcom,msm-adsp-loader {
status = "ok";
compatible = "qcom,adsp-loader";
qcom,adsp-state = <0>;
};
qcom,msm-audio-ion { qcom,msm-audio-ion {
compatible = "qcom,msm-audio-ion"; compatible = "qcom,msm-audio-ion";
@ -929,4 +939,35 @@
<86 512 0 0>, <86 512 0 0>,
<86 512 500 800>; <86 512 500 800>;
}; };
qcom,lpass@9300000 {
compatible = "qcom,pil-tz-generic";
reg = <0x9300000 0x00100>;
interrupts = <0 162 1>;
vdd_cx-supply = <&pm8994_s1_corner>;
qcom,proxy-reg-names = "vdd_cx";
qcom,vdd_cx-uV-uA = <7 100000>;
clocks = <&clock_gcc clk_cxo_pil_lpass_clk>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <1>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <423>;
qcom,sysmon-id = <1>;
qcom,ssctl-instance-id = <0x14>;
qcom,firmware-name = "adsp";
qcom,edge = "lpass";
memory-region = <&peripheral_mem>;
/* GPIO inputs from lpass */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
/* GPIO output to lpass */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
};
}; };