x86: merge apic_32/64.h
Unify apic.h variants. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Thomas Gleixner
Ingo Molnar
parent
42e0a9aa5d
commit
67c5fc5c33
3 changed files with 137 additions and 220 deletions
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@ -1,5 +1,139 @@
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#ifdef CONFIG_X86_32
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#ifndef _ASM_X86_APIC_H
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# include "apic_32.h"
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#define _ASM_X86_APIC_H
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#include <linux/pm.h>
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#include <linux/delay.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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extern void generic_apic_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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extern int apic_verbosity;
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extern int timer_over_8254;
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extern int local_apic_timer_c2_ok;
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extern int local_apic_timer_disabled;
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extern int apic_runs_main_timer;
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extern int ioapic_force;
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extern int disable_apic_timer;
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extern unsigned boot_cpu_id;
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#else
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# include "apic_64.h"
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#define apic_write native_apic_write
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#define apic_write_atomic native_apic_write_atomic
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#define apic_read native_apic_read
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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#endif
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#endif
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static inline fastcall void native_apic_write(unsigned long reg, u32 v)
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{
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*((volatile u32 *)(APIC_BASE + reg)) = v;
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}
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static inline fastcall void native_apic_write_atomic(unsigned long reg, u32 v)
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{
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(void) xchg((u32*)(APIC_BASE + reg), v);
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}
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static inline fastcall u32 native_apic_read(unsigned long reg)
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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extern void apic_wait_icr_idle(void);
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extern u32 safe_apic_wait_icr_idle(void);
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extern int get_physical_broadcast(void);
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define apic_read_around(x)
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# define apic_write_around(x, y) apic_write((x), (y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x, y) apic_write_atomic((x), (y))
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#endif
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write_around(APIC_EOI, 0);
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}
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern int verify_local_APIC(void);
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extern void cache_APIC_registers(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void setup_local_APIC(void);
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extern void init_apic_mappings(void);
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extern void smp_local_timer_interrupt(void);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern int APIC_init_uniprocessor(void);
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extern void enable_NMI_through_LVT0(void *dummy);
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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extern void setup_apic_routing(void);
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#endif
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extern void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector,
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unsigned char msg_type, unsigned char mask);
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extern int apic_is_clustered_box(void);
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#endif /* __ASM_APIC_H */
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@ -1,122 +0,0 @@
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#ifndef __ASM_APIC_H
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#define __ASM_APIC_H
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#include <linux/pm.h>
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#include <linux/delay.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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extern void generic_apic_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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extern int apic_verbosity;
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extern int timer_over_8254;
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extern int local_apic_timer_c2_ok;
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extern int local_apic_timer_disabled;
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define apic_write native_apic_write
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#define apic_write_atomic native_apic_write_atomic
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#define apic_read native_apic_read
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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#endif
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static __inline fastcall void native_apic_write(unsigned long reg, u32 v)
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{
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*((volatile u32 *)(APIC_BASE + reg)) = v;
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}
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static __inline fastcall void native_apic_write_atomic(unsigned long reg, u32 v)
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{
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(void) xchg((u32 *)(APIC_BASE + reg), v);
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}
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static __inline fastcall u32 native_apic_read(unsigned long reg)
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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extern void apic_wait_icr_idle(void);
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extern u32 safe_apic_wait_icr_idle(void);
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extern int get_physical_broadcast(void);
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define apic_read_around(x)
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# define apic_write_around(x,y) apic_write((x),(y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x,y) apic_write_atomic((x),(y))
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#endif
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write_around(APIC_EOI, 0);
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}
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern int verify_local_APIC(void);
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extern void cache_APIC_registers(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void setup_local_APIC(void);
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extern void init_apic_mappings(void);
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extern void smp_local_timer_interrupt(void);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern int APIC_init_uniprocessor(void);
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extern void enable_NMI_through_LVT0(void *dummy);
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#endif /* __ASM_APIC_H */
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@ -1,95 +0,0 @@
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#ifndef __ASM_APIC_H
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#define __ASM_APIC_H
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#include <linux/pm.h>
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#include <linux/delay.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/system.h>
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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extern int apic_verbosity;
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extern int apic_runs_main_timer;
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extern int ioapic_force;
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extern int disable_apic_timer;
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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struct pt_regs;
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/*
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* Basic functions accessing APICs.
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*/
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static __inline void apic_write(unsigned long reg, u32 v)
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{
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*((volatile unsigned int *)(APIC_BASE+reg)) = v;
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}
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static __inline u32 apic_read(unsigned long reg)
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{
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return *((volatile u32 *)(APIC_BASE+reg));
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}
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extern void apic_wait_icr_idle(void);
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extern u32 safe_apic_wait_icr_idle(void);
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write(APIC_EOI, 0);
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}
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern int verify_local_APIC(void);
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extern void cache_APIC_registers(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void setup_local_APIC(void);
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extern void init_apic_mappings(void);
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extern void smp_local_timer_interrupt(void);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern int APIC_init_uniprocessor(void);
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extern void setup_apic_routing(void);
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extern void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector,
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unsigned char msg_type, unsigned char mask);
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extern int apic_is_clustered_box(void);
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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extern unsigned boot_cpu_id;
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extern int local_apic_timer_c2_ok;
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#endif /* __ASM_APIC_H */
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