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[media] drxd: Run lindent across sources

Browse source 
Take a first cleanup pass over the sources to bring them closer to the
Linux coding style.

Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Devin Heitmueller 2011-03-24 13:44:01 -03:00 • committed by Mauro Carvalho Chehab
parent 9b316d6b42
commit 6cacdd46e2
5 changed files with 1753 additions and 3609 deletions
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3
drivers/media/dvb/frontends/drxd.h
View file

@ -27,8 +27,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/i2c.h> #include <linux/i2c.h>
struct drxd_config struct drxd_config {
{
u8 index; u8 index;
u8 pll_address; u8 pll_address;

150
drivers/media/dvb/frontends/drxd_firm.c
View file

@ -46,8 +46,7 @@
#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ #define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
u8_t DRXD_InitAtomicRead[] = u8_t DRXD_InitAtomicRead[] = {
{
WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE), WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
0x26, 0x00, /* 0 -> ring.rdy; */ 0x26, 0x00, /* 0 -> ring.rdy; */
0x60, 0x04, /* r0rami.dt -> ring.xba; */ 0x60, 0x04, /* r0rami.dt -> ring.xba; */
@ -68,8 +67,7 @@ u8_t DRXD_InitAtomicRead[] =
#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
/* D0 Version */ /* D0 Version */
u8_t DRXD_HiI2cPatch_1[] = u8_t DRXD_HiI2cPatch_1[] = {
{
WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
@ -115,10 +113,14 @@ u8_t DRXD_HiI2cPatch_1[] =
0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
/* Force quick and dirty reset */ /* Force quick and dirty reset */
WR16(B_HI_CT_REG_COMM_STATE__A, 0), WR16(B_HI_CT_REG_COMM_STATE__A, 0),
@ -126,8 +128,7 @@ u8_t DRXD_HiI2cPatch_1[] =
}; };
/* D0,D1 Version */ /* D0,D1 Version */
u8_t DRXD_HiI2cPatch_3[] = u8_t DRXD_HiI2cPatch_3[] = {
{
WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
@ -173,18 +174,21 @@ u8_t DRXD_HiI2cPatch_3[] =
0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
/* Force quick and dirty reset */ /* Force quick and dirty reset */
WR16(B_HI_CT_REG_COMM_STATE__A, 0), WR16(B_HI_CT_REG_COMM_STATE__A, 0),
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_ResetCEFR[] = u8_t DRXD_ResetCEFR[] = {
{
WRBLOCK(CE_REG_FR_TREAL00__A, 57), WRBLOCK(CE_REG_FR_TREAL00__A, 57),
0x52, 0x00, /* CE_REG_FR_TREAL00__A */ 0x52, 0x00, /* CE_REG_FR_TREAL00__A */
0x00, 0x00, /* CE_REG_FR_TIMAG00__A */ 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
@ -251,9 +255,7 @@ u8_t DRXD_ResetCEFR[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitFEA2_1[] = {
u8_t DRXD_InitFEA2_1[] =
{
WRBLOCK(FE_AD_REG_PD__A, 3), WRBLOCK(FE_AD_REG_PD__A, 3),
0x00, 0x00, /* FE_AD_REG_PD__A */ 0x00, 0x00, /* FE_AD_REG_PD__A */
0x01, 0x00, /* FE_AD_REG_INVEXT__A */ 0x01, 0x00, /* FE_AD_REG_INVEXT__A */
@ -339,8 +341,7 @@ u8_t DRXD_InitFEA2_1[] =
/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
u8_t DRXD_InitFEA2_2[] = u8_t DRXD_InitFEA2_2[] = {
{
WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
WR16(FE_AG_REG_FGM_WRI__A, 48), WR16(FE_AG_REG_FGM_WRI__A, 48),
/* Activate measurement, activate scale */ /* Activate measurement, activate scale */
@ -358,8 +359,7 @@ u8_t DRXD_InitFEA2_2[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitFEB1_1[] = u8_t DRXD_InitFEB1_1[] = {
{
WR16(B_FE_AD_REG_PD__A, 0x0000), WR16(B_FE_AD_REG_PD__A, 0x0000),
WR16(B_FE_AD_REG_CLKNEG__A, 0x0000), WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000), WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
@ -373,6 +373,7 @@ u8_t DRXD_InitFEB1_1[] =
WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7), WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
END_OF_TABLE END_OF_TABLE
}; };
/* with PGA */ /* with PGA */
/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */ /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
/* without PGA */ /* without PGA */
@ -381,8 +382,7 @@ u8_t DRXD_InitFEB1_1[] =
/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */ /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
u8_t DRXD_InitFEB1_2[] = u8_t DRXD_InitFEB1_2[] = {
{
WR16(B_FE_COMM_EXEC__A, 0x0001), WR16(B_FE_COMM_EXEC__A, 0x0001),
/* RF-AGC setup */ /* RF-AGC setup */
@ -404,8 +404,7 @@ u8_t DRXD_InitFEB1_2[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitCPA2[] = u8_t DRXD_InitCPA2[] = {
{
WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2), WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */ 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */ 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
@ -435,16 +434,13 @@ u8_t DRXD_InitCPA2[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitCPB1[] = u8_t DRXD_InitCPB1[] = {
{
WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008), WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
WR16(B_CP_COMM_EXEC__A, 0x0001), WR16(B_CP_COMM_EXEC__A, 0x0001),
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitCEA2[] = {
u8_t DRXD_InitCEA2[] =
{
WRBLOCK(CE_REG_AVG_POW__A, 4), WRBLOCK(CE_REG_AVG_POW__A, 4),
0x62, 0x00, /* CE_REG_AVG_POW__A */ 0x62, 0x00, /* CE_REG_AVG_POW__A */
0x78, 0x00, /* CE_REG_MAX_POW__A */ 0x78, 0x00, /* CE_REG_MAX_POW__A */
@ -482,22 +478,19 @@ u8_t DRXD_InitCEA2[] =
0x00, 0x00, /* CE_REG_IR_STARTPOS__A */ 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */ 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000), WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitCEB1[] = u8_t DRXD_InitCEB1[] = {
{
WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001), WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
WR16(B_CE_REG_FR_PM_SET__A, 0x000D), WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitEQA2[] = u8_t DRXD_InitEQA2[] = {
{
WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4), WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */ 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */ 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
@ -512,14 +505,12 @@ u8_t DRXD_InitEQA2[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitEQB1[] = u8_t DRXD_InitEQB1[] = {
{
WR16(B_EQ_REG_COMM_EXEC__A, 0x0001), WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_ResetECRAM[] = u8_t DRXD_ResetECRAM[] = {
{
/* Reset packet sync bytes in EC_VD ram */ /* Reset packet sync bytes in EC_VD ram */
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
@ -539,8 +530,7 @@ u8_t DRXD_ResetECRAM[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitECA2[] = u8_t DRXD_InitECA2[] = {
{
WRBLOCK(EC_SB_REG_CSI_HI__A, 6), WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */ 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */ 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
@ -626,8 +616,7 @@ u8_t DRXD_InitECA2[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitECB1[] = u8_t DRXD_InitECB1[] = {
{
WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001), WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001), WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001), WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
@ -682,8 +671,7 @@ u8_t DRXD_InitECB1[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_ResetECA2[] = u8_t DRXD_ResetECA2[] = {
{
WR16(EC_OC_REG_COMM_EXEC__A, 0x0000), WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
WR16(EC_OD_REG_COMM_EXEC__A, 0x0000), WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
@ -754,8 +742,7 @@ u8_t DRXD_ResetECA2[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitSC[] = u8_t DRXD_InitSC[] = {
{
WR16(SC_COMM_EXEC__A, 0), WR16(SC_COMM_EXEC__A, 0),
WR16(SC_COMM_STATE__A, 0), WR16(SC_COMM_STATE__A, 0),
@ -769,8 +756,7 @@ u8_t DRXD_InitSC[] =
/* Diversity settings */ /* Diversity settings */
u8_t DRXD_InitDiversityFront[] = u8_t DRXD_InitDiversityFront[] = {
{
/* Start demod ********* RF in , diversity out **************************** */ /* Start demod ********* RF in , diversity out **************************** */
WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
B_SC_RA_RAM_CONFIG_FREQSCAN__M), B_SC_RA_RAM_CONFIG_FREQSCAN__M),
@ -800,17 +786,14 @@ u8_t DRXD_InitDiversityFront[] =
WR16(B_CC_REG_DIVERSITY__A, 0x0001), WR16(B_CC_REG_DIVERSITY__A, 0x0001),
WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010), WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
/* 0x2a ), *//* CE to PASS mux */ /* 0x2a ), *//* CE to PASS mux */
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_InitDiversityEnd[] = u8_t DRXD_InitDiversityEnd[] = {
{
/* End demod *********** combining RF in and diversity in, MPEG TS out **** */ /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
/* disable near/far; switch on timing slave mode */ /* disable near/far; switch on timing slave mode */
WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
@ -852,23 +835,34 @@ u8_t DRXD_InitDiversityEnd[] =
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_DisableDiversity[] = u8_t DRXD_DisableDiversity[] = {
{
WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ), WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ), B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ), WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ), B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ), WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ), B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ), WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ), B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ), WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ), B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ), WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ), B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE), WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE), WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
@ -876,31 +870,27 @@ u8_t DRXD_DisableDiversity[] =
WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE), WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE), WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
WR16(B_CC_REG_DIVERSITY__A, 0x0000), WR16(B_CC_REG_DIVERSITY__A, 0x0000),
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */ WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_StartDiversityFront[] = u8_t DRXD_StartDiversityFront[] = {
{
/* Start demod, RF in and diversity out, no combining */ /* Start demod, RF in and diversity out, no combining */
WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
WR16(B_FE_AD_REG_FDB_IN__A, 0x0), WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
WR16(B_FE_AD_REG_INVEXT__A, 0x0), WR16(B_FE_AD_REG_INVEXT__A, 0x0),
WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */ WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */ WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2), WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_StartDiversityEnd[] = u8_t DRXD_StartDiversityEnd[] = {
{
/* End demod, combining RF in and diversity in, MPEG TS out */ /* End demod, combining RF in and diversity in, MPEG TS out */
WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */ WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */ WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
@ -908,14 +898,12 @@ u8_t DRXD_StartDiversityEnd[] =
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */ WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ),
END_OF_TABLE END_OF_TABLE
}; };
u8_t DRXD_DiversityDelay8MHZ[] = u8_t DRXD_DiversityDelay8MHZ[] = {
{
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50), WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50), WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50), WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),

2
drivers/media/dvb/frontends/drxd_firm.h
View file

@ -65,7 +65,6 @@ typedef unsigned long u32_t;
#define DRXD_SCAN_TIMEOUT (650) #define DRXD_SCAN_TIMEOUT (650)
#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
@ -78,7 +77,6 @@ typedef unsigned long u32_t;
#define DIFF_TARGET (4) #define DIFF_TARGET (4)
#define DIFF_MARGIN (1) #define DIFF_MARGIN (1)
extern u8_t DRXD_InitAtomicRead[]; extern u8_t DRXD_InitAtomicRead[];
extern u8_t DRXD_HiI2cPatch_1[]; extern u8_t DRXD_HiI2cPatch_1[];
extern u8_t DRXD_HiI2cPatch_3[]; extern u8_t DRXD_HiI2cPatch_3[];

279
drivers/media/dvb/frontends/drxd_hard.c
View file

@ -62,7 +62,6 @@
#define DRX_LOCK_FEC 2 #define DRX_LOCK_FEC 2
#define DRX_LOCK_DEMOD 4 #define DRX_LOCK_DEMOD 4
/****************************************************************************/ /****************************************************************************/
enum CSCDState { enum CSCDState {
@ -205,7 +204,6 @@ struct drxd_state {
}; };
/****************************************************************************/ /****************************************************************************/
/* I2C **********************************************************************/ /* I2C **********************************************************************/
/****************************************************************************/ /****************************************************************************/
@ -225,7 +223,8 @@ static int i2c_read(struct i2c_adapter *adap,
struct i2c_msg msgs[2] = { {.addr = adr,.flags = 0, struct i2c_msg msgs[2] = { {.addr = adr,.flags = 0,
.buf = msg,.len = len}, .buf = msg,.len = len},
{.addr = adr,.flags = I2C_M_RD, {.addr = adr,.flags = I2C_M_RD,
.buf=answ, .len=alen } }; .buf = answ,.len = alen}
};
if (i2c_transfer(adap, msgs, 2) != 2) if (i2c_transfer(adap, msgs, 2) != 2)
return -1; return -1;
return 0; return 0;
@ -245,7 +244,8 @@ static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
{ {
u8 adr = state->config.demod_address; u8 adr = state->config.demod_address;
u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
flags|((reg>>24)&0xff), (reg>>8)&0xff}; flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
};
u8 mm2[2]; u8 mm2[2];
if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
return -1; return -1;
@ -258,13 +258,15 @@ static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
{ {
u8 adr = state->config.demod_address; u8 adr = state->config.demod_address;
u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
flags|((reg>>24)&0xff), (reg>>8)&0xff}; flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
};
u8 mm2[4]; u8 mm2[4];
if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
return -1; return -1;
if (data) if (data)
*data=mm2[0]|(mm2[1]<<8)|(mm2[2]<<16)|(mm2[3]<<24); *data =
mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
return 0; return 0;
} }
@ -273,7 +275,8 @@ static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
u8 adr = state->config.demod_address; u8 adr = state->config.demod_address;
u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
data&0xff, (data>>8)&0xff }; data & 0xff, (data >> 8) & 0xff
};
if (i2c_write(state->i2c, adr, mm, 6) < 0) if (i2c_write(state->i2c, adr, mm, 6) < 0)
return -1; return -1;
@ -286,7 +289,8 @@ static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
data & 0xff, (data >> 8) & 0xff, data & 0xff, (data >> 8) & 0xff,
(data>>16)&0xff, (data>>24)&0xff }; (data >> 16) & 0xff, (data >> 24) & 0xff
};
if (i2c_write(state->i2c, adr, mm, 8) < 0) if (i2c_write(state->i2c, adr, mm, 8) < 0)
return -1; return -1;
@ -298,7 +302,8 @@ static int write_chunk(struct drxd_state *state,
{ {
u8 adr = state->config.demod_address; u8 adr = state->config.demod_address;
u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
flags|((reg>>24)&0xff), (reg>>8)&0xff }; flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
};
int i; int i;
for (i = 0; i < len; i++) for (i = 0; i < len; i++)
@ -351,7 +356,6 @@ static int WriteTable(struct drxd_state *state, u8 *pTable)
return status; return status;
} }
/****************************************************************************/ /****************************************************************************/
/****************************************************************************/ /****************************************************************************/
/****************************************************************************/ /****************************************************************************/
@ -513,8 +517,7 @@ static int DRX_GetLockStatus(struct drxd_state *state, u32 *pLockStatus)
status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
if (status < 0) { if (status < 0) {
printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
status);
return status; return status;
} }
@ -550,10 +553,8 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
&FeAgRegAgModeLop, 0)); &FeAgRegAgModeLop, 0));
FeAgRegAgModeLop &= FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
(~FE_AG_REG_AG_MODE_LOP_MODE_4__M); FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
FeAgRegAgModeLop |=
FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
FeAgRegAgModeLop, 0)); FeAgRegAgModeLop, 0));
@ -579,8 +580,7 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
&FeAgRegAgModeLop, 0)); &FeAgRegAgModeLop, 0));
FeAgRegAgModeLop &= FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
(~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
FeAgRegAgModeLop |= FeAgRegAgModeLop |=
FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
@ -613,7 +613,8 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
17, 18, 18, 19, 17, 18, 18, 19,
20, 21, 22, 23, 20, 21, 22, 23,
24, 26, 27, 28, 24, 26, 27, 28,
29, 31}; 29, 31
};
u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) / u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
(maxRur + 1); (maxRur + 1);
@ -624,8 +625,7 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
u16 invRurCount = (u16) (cfg->speed / u16 invRurCount = (u16) (cfg->speed /
fineSteps); fineSteps);
u16 rurCount; u16 rurCount;
if ( invRurCount > maxRur ) if (invRurCount > maxRur) {
{
rurCount = 0; rurCount = 0;
fineSpeed += fineSteps; fineSpeed += fineSteps;
} else { } else {
@ -644,8 +644,10 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
fastIncrDecLUT[fineSpeed / fastIncrDecLUT[fineSpeed /
((fineSteps / ((fineSteps /
(14 + 1)) + 1)]; (14 + 1)) + 1)];
u16 slowIncrDec = slowIncrDecLUT[ u16 slowIncrDec =
fineSpeed/(fineSteps/(3+1)) ]; slowIncrDecLUT[fineSpeed /
(fineSteps /
(3 + 1))];
CHK_ERROR(Write16(state, CHK_ERROR(Write16(state,
FE_AG_REG_EGC_RUR_CNT__A, FE_AG_REG_EGC_RUR_CNT__A,
@ -673,7 +675,6 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
return status; return status;
} }
static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
{ {
int status = 0; int status = 0;
@ -695,8 +696,7 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
/*==== Mode ====*/ /*==== Mode ====*/
/* Powerdown PD2, WRI source */ /* Powerdown PD2, WRI source */
state->m_FeAgRegAgPwd &= state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
~(FE_AG_REG_AG_PWD_PWD_PD2__M);
state->m_FeAgRegAgPwd |= state->m_FeAgRegAgPwd |=
FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A,
@ -711,7 +711,6 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
AgModeLop, 0x0000)); AgModeLop, 0x0000));
/* enable AGC2 pin */ /* enable AGC2 pin */
{ {
u16 FeAgRegAgAgcSio = 0; u16 FeAgRegAgAgcSio = 0;
@ -891,23 +890,29 @@ static int DownloadMicrocode(struct drxd_state *state,
pSrc = (u8 *) pMCImage; pSrc = (u8 *) pMCImage;
Flags = (pSrc[0] << 8) | pSrc[1]; Flags = (pSrc[0] << 8) | pSrc[1];
pSrc += sizeof(u16); offset += sizeof(u16); pSrc += sizeof(u16);
offset += sizeof(u16);
nBlocks = (pSrc[0] << 8) | pSrc[1]; nBlocks = (pSrc[0] << 8) | pSrc[1];
pSrc += sizeof(u16); offset += sizeof(u16); pSrc += sizeof(u16);
offset += sizeof(u16);
for (i = 0; i < nBlocks; i++) { for (i = 0; i < nBlocks; i++) {
Address = (pSrc[0] << 24) | (pSrc[1] << 16) | Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
(pSrc[2] << 8) | pSrc[3]; (pSrc[2] << 8) | pSrc[3];
pSrc += sizeof(u32); offset += sizeof(u32); pSrc += sizeof(u32);
offset += sizeof(u32);
BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
pSrc += sizeof(u16); offset += sizeof(u16); pSrc += sizeof(u16);
offset += sizeof(u16);
Flags = (pSrc[0] << 8) | pSrc[1]; Flags = (pSrc[0] << 8) | pSrc[1];
pSrc += sizeof(u16); offset += sizeof(u16); pSrc += sizeof(u16);
offset += sizeof(u16);
BlockCRC = (pSrc[0] << 8) | pSrc[1]; BlockCRC = (pSrc[0] << 8) | pSrc[1];
pSrc += sizeof(u16); offset += sizeof(u16); pSrc += sizeof(u16);
offset += sizeof(u16);
status = WriteBlock(state, Address, BlockSize, status = WriteBlock(state, Address, BlockSize,
pSrc, DRX_I2C_CLEARCRC); pSrc, DRX_I2C_CLEARCRC);
@ -948,16 +953,13 @@ static int HI_CfgCommand(struct drxd_state *state)
int status = 0; int status = 0;
down(&state->mutex); down(&state->mutex);
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
HI_RA_RAM_SRV_RST_KEY_ACT, 0);
Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
state->hi_cfg_bridge_delay, 0);
Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
HI_RA_RAM_SRV_RST_KEY_ACT, 0);
if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
@ -991,8 +993,7 @@ static int HI_ResetCommand(struct drxd_state *state)
return status; return status;
} }
static int DRX_ConfigureI2CBridge(struct drxd_state *state, static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
int bEnableBridge)
{ {
state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
if (bEnableBridge) if (bEnableBridge)
@ -1066,8 +1067,7 @@ static int AtomicReadReg32(struct drxd_state *state,
status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags); status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
*pData = (((u32) buf[0]) << 0) + *pData = (((u32) buf[0]) << 0) +
(((u32) buf[1]) << 8) + (((u32) buf[1]) << 8) +
(((u32) buf[2]) << 16) + (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
(((u32) buf[3]) << 24);
return status; return status;
} }
#endif #endif
@ -1126,7 +1126,6 @@ static int ResetECOD(struct drxd_state *state)
return status; return status;
} }
/* Configure PGA switch */ /* Configure PGA switch */
static int SetCfgPga(struct drxd_state *state, int pgaSwitch) static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
@ -1192,31 +1191,33 @@ static int InitFE(struct drxd_state *state)
{ {
int status; int status;
do do {
{
CHK_ERROR(WriteTable(state, state->m_InitFE_1)); CHK_ERROR(WriteTable(state, state->m_InitFE_1));
if (state->type_A) { if (state->type_A) {
status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0); FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
0);
} else { } else {
if (state->PGA) if (state->PGA)
status = SetCfgPga(state, 0); status = SetCfgPga(state, 0);
else else
status = status =
Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0); B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
0);
} }
if (status<0) break; if (status < 0)
break;
CHK_ERROR(Write16(state, FE_AG_REG_AG_AGC_SIO__A, CHK_ERROR(Write16(state, FE_AG_REG_AG_AGC_SIO__A,
state->m_FeAgRegAgAgcSio, 0x0000)); state->m_FeAgRegAgAgcSio, 0x0000));
CHK_ERROR( Write16( state, FE_AG_REG_AG_PWD__A,state->m_FeAgRegAgPwd, CHK_ERROR(Write16
(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd,
0x0000)); 0x0000));
CHK_ERROR(WriteTable(state, state->m_InitFE_2)); CHK_ERROR(WriteTable(state, state->m_InitFE_2));
} while (0); } while (0);
return status; return status;
@ -1236,8 +1237,7 @@ static int SC_WaitForReady(struct drxd_state *state)
u16 curCmd; u16 curCmd;
int i; int i;
for(i = 0; i < DRXD_MAX_RETRIES; i += 1 ) for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
{
int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
if (status == 0 || curCmd == 0) if (status == 0 || curCmd == 0)
return status; return status;
@ -1255,8 +1255,7 @@ static int SC_SendCommand(struct drxd_state *state, u16 cmd)
Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
if( errCode == 0xFFFF ) if (errCode == 0xFFFF) {
{
printk("Command Error\n"); printk("Command Error\n");
status = -1; status = -1;
} }
@ -1288,7 +1287,6 @@ static int SC_ProcStartCommand(struct drxd_state *state,
return status; return status;
} }
static int SC_SetPrefParamCommand(struct drxd_state *state, static int SC_SetPrefParamCommand(struct drxd_state *state,
u16 subCmd, u16 param0, u16 param1) u16 subCmd, u16 param0, u16 param1)
{ {
@ -1301,8 +1299,7 @@ static int SC_SetPrefParamCommand(struct drxd_state *state,
CHK_ERROR(Write16(state, SC_RA_RAM_PARAM1__A, param1, 0)); CHK_ERROR(Write16(state, SC_RA_RAM_PARAM1__A, param1, 0));
CHK_ERROR(Write16(state, SC_RA_RAM_PARAM0__A, param0, 0)); CHK_ERROR(Write16(state, SC_RA_RAM_PARAM0__A, param0, 0));
CHK_ERROR( SC_SendCommand(state, CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM));
SC_RA_RAM_CMD_SET_PREF_PARAM) );
} while (0); } while (0);
up(&state->mutex); up(&state->mutex);
return status; return status;
@ -1316,8 +1313,7 @@ static int SC_GetOpParamCommand(struct drxd_state *state, u16 *result)
down(&state->mutex); down(&state->mutex);
do { do {
CHK_ERROR(SC_WaitForReady(state)); CHK_ERROR(SC_WaitForReady(state));
CHK_ERROR( SC_SendCommand(state, CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM));
SC_RA_RAM_CMD_GET_OP_PARAM) );
CHK_ERROR(Read16(state, SC_RA_RAM_PARAM0__A, result, 0)); CHK_ERROR(Read16(state, SC_RA_RAM_PARAM0__A, result, 0));
} while (0); } while (0);
up(&state->mutex); up(&state->mutex);
@ -1338,31 +1334,24 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
/*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A,
&EcOcRegOcModeLop, 0)); */ &EcOcRegOcModeLop, 0)); */
if( state->operation_mode == OM_DVBT_Diversity_Front ) if (state->operation_mode == OM_DVBT_Diversity_Front) {
{ if (bEnableOutput) {
if ( bEnableOutput )
{
EcOcRegOcModeHip |= EcOcRegOcModeHip |=
B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
} } else
else
EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
EcOcRegOcModeLop |= EcOcRegOcModeLop |=
EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
} } else {
else
{
EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
if (bEnableOutput) if (bEnableOutput)
EcOcRegOcMpgSio &= EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
(~(EC_OC_REG_OC_MPG_SIO__M));
else else
EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
/* Don't Insert RS Byte */ /* Don't Insert RS Byte */
if( state->insert_rs_byte ) if (state->insert_rs_byte) {
{
EcOcRegOcModeLop &= EcOcRegOcModeLop &=
(~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
EcOcRegOcModeHip &= EcOcRegOcModeHip &=
@ -1525,21 +1514,17 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
causes trouble (at least for diversity */ causes trouble (at least for diversity */
CHK_ERROR(Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, CHK_ERROR(Read32(state, LC_RA_RAM_IFINCR_NOM_L__A,
((u32 *) & nomincr), 0)); ((u32 *) & nomincr), 0));
CHK_ERROR( Read32(state, FE_IF_REG_INCR0__A, CHK_ERROR(Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0));
(u32 *) &incr,0 ));
if (state->type_A) { if (state->type_A) {
if( (nomincr - incr < -500) || if ((nomincr - incr < -500) || (nomincr - incr > 500))
(nomincr - incr > 500 ) )
break; break;
} else { } else {
if( (nomincr - incr < -2000 ) || if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
(nomincr - incr > 2000 ) )
break; break;
} }
switch( state->param.u.ofdm.bandwidth ) switch (state->param.u.ofdm.bandwidth) {
{
case BANDWIDTH_8_MHZ: case BANDWIDTH_8_MHZ:
bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
break; break;
@ -1560,27 +1545,27 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21); sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
sysClockFreq = (u32) (sysClockInHz / 1000); sysClockFreq = (u32) (sysClockInHz / 1000);
/* rounding */ /* rounding */
if ( ( sysClockInHz%1000 ) > 500 ) if ((sysClockInHz % 1000) > 500) {
{
sysClockFreq++; sysClockFreq++;
} }
/* Compute clock deviation in ppm */ /* Compute clock deviation in ppm */
oscClockDeviation = (u16) ( oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
(((s32)(sysClockFreq) - (s32)
(s32)(state->expected_sys_clock_freq))* (state->expected_sys_clock_freq)) *
1000000L)/(s32)(state->expected_sys_clock_freq) ); 1000000L) /
(s32)
(state->expected_sys_clock_freq));
Diff = oscClockDeviation - state->osc_clock_deviation; Diff = oscClockDeviation - state->osc_clock_deviation;
/*printk("sysclockdiff=%d\n", Diff); */ /*printk("sysclockdiff=%d\n", Diff); */
if (Diff >= -200 && Diff <= 200) { if (Diff >= -200 && Diff <= 200) {
state->sys_clock_freq = (u16) sysClockFreq; state->sys_clock_freq = (u16) sysClockFreq;
if( oscClockDeviation != if (oscClockDeviation != state->osc_clock_deviation) {
state->osc_clock_deviation ) {
if (state->config.osc_deviation) { if (state->config.osc_deviation) {
state->config.osc_deviation( state->config.osc_deviation(state->priv,
state->priv, oscClockDeviation,
oscClockDeviation, 1); 1);
state->osc_clock_deviation = state->osc_clock_deviation =
oscClockDeviation; oscClockDeviation;
} }
@ -1649,15 +1634,13 @@ static int DRX_Stop(struct drxd_state *state)
B_EQ_COMM_EXEC__A, B_EQ_COMM_EXEC__A,
SC_COMM_EXEC_CTL_STOP, 0)); SC_COMM_EXEC_CTL_STOP, 0));
CHK_ERROR(Write16(state, CHK_ERROR(Write16(state,
EC_OD_REG_COMM_EXEC__A, EC_OD_REG_COMM_EXEC__A, 0x0000, 0));
0x0000, 0 ));
} }
} while (0); } while (0);
return status; return status;
} }
int SetOperationMode(struct drxd_state *state, int oMode) int SetOperationMode(struct drxd_state *state, int oMode)
{ {
int status; int status;
@ -1678,15 +1661,12 @@ int SetOperationMode(struct drxd_state *state, int oMode)
break; break;
} }
switch(oMode) switch (oMode) {
{
case OM_DVBT_Diversity_Front: case OM_DVBT_Diversity_Front:
status = WriteTable(state, status = WriteTable(state, state->m_InitDiversityFront);
state->m_InitDiversityFront);
break; break;
case OM_DVBT_Diversity_End: case OM_DVBT_Diversity_End:
status = WriteTable(state, status = WriteTable(state, state->m_InitDiversityEnd);
state->m_InitDiversityEnd);
break; break;
case OM_Default: case OM_Default:
/* We need to check how to /* We need to check how to
@ -1702,8 +1682,6 @@ int SetOperationMode(struct drxd_state *state, int oMode)
return status; return status;
} }
static int StartDiversity(struct drxd_state *state) static int StartDiversity(struct drxd_state *state)
{ {
int status = 0; int status = 0;
@ -1716,15 +1694,12 @@ static int StartDiversity(struct drxd_state *state)
} else if (state->operation_mode == OM_DVBT_Diversity_End) { } else if (state->operation_mode == OM_DVBT_Diversity_End) {
CHK_ERROR(WriteTable(state, CHK_ERROR(WriteTable(state,
state->m_StartDiversityEnd)); state->m_StartDiversityEnd));
if( state->param.u.ofdm.bandwidth == if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
BANDWIDTH_8_MHZ ) { CHK_ERROR(WriteTable(state,
CHK_ERROR(
WriteTable(state,
state-> state->
m_DiversityDelay8MHZ)); m_DiversityDelay8MHZ));
} else { } else {
CHK_ERROR( CHK_ERROR(WriteTable(state,
WriteTable(state,
state-> state->
m_DiversityDelay6MHZ)); m_DiversityDelay6MHZ));
} }
@ -1746,7 +1721,6 @@ static int StartDiversity(struct drxd_state *state)
return status; return status;
} }
static int SetFrequencyShift(struct drxd_state *state, static int SetFrequencyShift(struct drxd_state *state,
u32 offsetFreq, int channelMirrored) u32 offsetFreq, int channelMirrored)
{ {
@ -1768,8 +1742,7 @@ static int SetFrequencyShift(struct drxd_state *state,
1 << 28, state->sys_clock_freq); 1 << 28, state->sys_clock_freq);
/* Remove integer part */ /* Remove integer part */
state->fe_fs_add_incr &= 0x0FFFFFFFL; state->fe_fs_add_incr &= 0x0FFFFFFFL;
if (negativeShift) if (negativeShift) {
{
state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
} }
@ -1794,21 +1767,17 @@ static int SetCfgNoiseCalibration (struct drxd_state *state,
int status = 0; int status = 0;
do { do {
CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0));
&beOptEna, 0)); if (noiseCal->cpOpt) {
if (noiseCal->cpOpt)
{
beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
} else { } else {
beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A, CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A,
noiseCal->cpNexpOfs, 0)); noiseCal->cpNexpOfs, 0));
} }
CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0));
beOptEna, 0));
if( !state->type_A ) if (!state->type_A) {
{
CHK_ERROR(Write16(state, CHK_ERROR(Write16(state,
B_SC_RA_RAM_CO_TD_CAL_2K__A, B_SC_RA_RAM_CO_TD_CAL_2K__A,
noiseCal->tdCal2k, 0)); noiseCal->tdCal2k, 0));
@ -1902,8 +1871,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
break; break;
} }
switch( p->guard_interval ) switch (p->guard_interval) {
{
case GUARD_INTERVAL_1_4: case GUARD_INTERVAL_1_4:
transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
break; break;
@ -1923,8 +1891,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
break; break;
} }
switch( p->hierarchy_information ) switch (p->hierarchy_information) {
{
case HIERARCHY_1: case HIERARCHY_1:
transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
if (state->type_A) { if (state->type_A) {
@ -2157,8 +2124,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
} }
switch( p->code_rate_HP ) switch (p->code_rate_HP) {
{
case FEC_1_2: case FEC_1_2:
transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
if (state->type_A) { if (state->type_A) {
@ -2216,8 +2182,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
by SC for fix for some 8K,1/8 guard but is restored by by SC for fix for some 8K,1/8 guard but is restored by
InitEC and ResetEC InitEC and ResetEC
functions */ functions */
switch( p->bandwidth ) switch (p->bandwidth) {
{
case BANDWIDTH_AUTO: case BANDWIDTH_AUTO:
case BANDWIDTH_8_MHZ: case BANDWIDTH_8_MHZ:
/* (64/7)*(8/8)*1000000 */ /* (64/7)*(8/8)*1000000 */
@ -2268,8 +2233,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
CHK_ERROR(SetCfgNoiseCalibration(state, &state->noise_cal)); CHK_ERROR(SetCfgNoiseCalibration(state, &state->noise_cal));
if (state->cscd_state == CSCD_INIT ) if (state->cscd_state == CSCD_INIT) {
{
/* switch on SRMM scan in SC */ /* switch on SRMM scan in SC */
CHK_ERROR(Write16(state, CHK_ERROR(Write16(state,
SC_RA_RAM_SAMPLE_RATE_COUNT__A, SC_RA_RAM_SAMPLE_RATE_COUNT__A,
@ -2279,7 +2243,6 @@ static int DRX_Start(struct drxd_state *state, s32 off)
state->cscd_state = CSCD_SET; state->cscd_state = CSCD_SET;
} }
/* Now compute FE_IF_REG_INCR */ /* Now compute FE_IF_REG_INCR */
/*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
((SysFreq / BandWidth) * (2^21) ) - (2^23) */ ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
@ -2370,8 +2333,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
state->if_agc_cfg.maxOutputLevel = 1023; state->if_agc_cfg.maxOutputLevel = 1023;
state->if_agc_cfg.speed = 904; state->if_agc_cfg.speed = 904;
if( ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX ) if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
{
state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
} }
@ -2380,9 +2342,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX && ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX && ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX && ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
ulIfAgcSpeed <= DRXD_FE_CTRL_MAX ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
)
{
state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
@ -2409,9 +2369,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX && ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX && ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX && ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
ulRfAgcSpeed <= DRXD_FE_CTRL_MAX ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
)
{
state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
@ -2419,8 +2377,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
} }
if( ulRfAgcMode == 2 ) if (ulRfAgcMode == 2) {
{
state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
} }
@ -2431,8 +2388,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
state->app_env_diversity = (enum app_env) state->app_env_diversity = (enum app_env)
(ulEnvironmentDiversity); (ulEnvironmentDiversity);
if( ulIFFilter == IFFILTER_DISCRETE ) if (ulIFFilter == IFFILTER_DISCRETE) {
{
/* discrete filter */ /* discrete filter */
state->noise_cal.cpOpt = 0; state->noise_cal.cpOpt = 0;
state->noise_cal.cpNexpOfs = 40; state->noise_cal.cpNexpOfs = 40;
@ -2448,10 +2404,13 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
state->chip_adr = (state->config.demod_address << 1) | 1; state->chip_adr = (state->config.demod_address << 1) | 1;
switch( ulHiI2cPatch ) switch (ulHiI2cPatch) {
{ case 1:
case 1 : state->m_HiI2cPatch = DRXD_HiI2cPatch_1; break; state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
case 3 : state->m_HiI2cPatch = DRXD_HiI2cPatch_3; break; break;
case 3:
state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
break;
default: default:
state->m_HiI2cPatch = NULL; state->m_HiI2cPatch = NULL;
} }
@ -2525,8 +2484,7 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
if (state->config.osc_deviation) if (state->config.osc_deviation)
state->osc_clock_deviation = state->osc_clock_deviation =
state->config.osc_deviation(state->priv, state->config.osc_deviation(state->priv, 0, 0);
0, 0);
{ {
/* Handle clock deviation */ /* Handle clock deviation */
s32 devB; s32 devB;
@ -2539,14 +2497,13 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
devB = (2); devB = (2);
else else
devB = (-2); devB = (-2);
if ( (devB*(devA%1000000L)>1000000L ) ) if ((devB * (devA % 1000000L) > 1000000L)) {
{
/* add +1 or -1 */ /* add +1 or -1 */
deviation += (devB / 2); deviation += (devB / 2);
} }
state->sys_clock_freq=(u16)((state-> state->sys_clock_freq =
expected_sys_clock_freq)+ (u16) ((state->expected_sys_clock_freq) +
deviation); deviation);
} }
CHK_ERROR(InitHI(state)); CHK_ERROR(InitHI(state));
@ -2589,15 +2546,13 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
CHK_ERROR(Write16(state, LC_COMM_EXEC__A, CHK_ERROR(Write16(state, LC_COMM_EXEC__A,
SC_COMM_EXEC_CTL_STOP, 0)); SC_COMM_EXEC_CTL_STOP, 0));
driverVersion = (((VERSION_MAJOR / 10) << 4) + driverVersion = (((VERSION_MAJOR / 10) << 4) +
(VERSION_MAJOR % 10)) << 24; (VERSION_MAJOR % 10)) << 24;
driverVersion += (((VERSION_MINOR / 10) << 4) + driverVersion += (((VERSION_MINOR / 10) << 4) +
(VERSION_MINOR % 10)) << 16; (VERSION_MINOR % 10)) << 16;
driverVersion += ((VERSION_PATCH / 1000) << 12) + driverVersion += ((VERSION_PATCH / 1000) << 12) +
((VERSION_PATCH / 100) << 8) + ((VERSION_PATCH / 100) << 8) +
((VERSION_PATCH/10 )<< 4) + ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
(VERSION_PATCH%10 );
CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX,
driverVersion, 0)); driverVersion, 0));
@ -2629,8 +2584,7 @@ int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
/****************************************************************************/ /****************************************************************************/
/****************************************************************************/ /****************************************************************************/
static int drxd_read_signal_strength(struct dvb_frontend *fe, static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
u16 *strength)
{ {
struct drxd_state *state = fe->demodulator_priv; struct drxd_state *state = fe->demodulator_priv;
u32 value; u32 value;
@ -2644,7 +2598,6 @@ static int drxd_read_signal_strength(struct dvb_frontend *fe,
return 0; return 0;
} }
static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status) static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
{ {
struct drxd_state *state = fe->demodulator_priv; struct drxd_state *state = fe->demodulator_priv;
@ -2756,8 +2709,7 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
if (state->config.pll_set && if (state->config.pll_set &&
state->config.pll_set(state->priv, param, state->config.pll_set(state->priv, param,
state->config.pll_address, state->config.pll_address,
state->config.demoda_address, state->config.demoda_address, &off) < 0) {
&off)<0) {
printk("Error in pll_set\n"); printk("Error in pll_set\n");
return -1; return -1;
} }
@ -2767,7 +2719,6 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
return DRX_Start(state, off); return DRX_Start(state, off);
} }
static void drxd_release(struct dvb_frontend *fe) static void drxd_release(struct dvb_frontend *fe)
{ {
struct drxd_state *state = fe->demodulator_priv; struct drxd_state *state = fe->demodulator_priv;
@ -2791,9 +2742,7 @@ static struct dvb_frontend_ops drxd_ops = {
FE_CAN_QAM_AUTO | FE_CAN_QAM_AUTO |
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
FE_CAN_MUTE_TS
},
.release = drxd_release, .release = drxd_release,
.init = drxd_init, .init = drxd_init,

1790
drivers/media/dvb/frontends/drxd_map_firm.h
View file

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