[media] drxd: Run lindent across sources
Take a first cleanup pass over the sources to bring them closer to the Linux coding style. Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Devin Heitmueller
Mauro Carvalho Chehab
parent
9b316d6b42
commit
6cacdd46e2
5 changed files with 1753 additions and 3609 deletions
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@ -27,8 +27,7 @@
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#include <linux/types.h>
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#include <linux/i2c.h>
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struct drxd_config
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{
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struct drxd_config {
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u8 index;
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u8 pll_address;
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@ -46,8 +46,7 @@
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#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
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#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
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u8_t DRXD_InitAtomicRead[] =
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{
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u8_t DRXD_InitAtomicRead[] = {
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WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
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0x26, 0x00, /* 0 -> ring.rdy; */
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0x60, 0x04, /* r0rami.dt -> ring.xba; */
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@ -68,8 +67,7 @@ u8_t DRXD_InitAtomicRead[] =
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#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
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/* D0 Version */
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u8_t DRXD_HiI2cPatch_1[] =
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{
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u8_t DRXD_HiI2cPatch_1[] = {
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WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
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0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
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0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
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@ -115,10 +113,14 @@ u8_t DRXD_HiI2cPatch_1[] =
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0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
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0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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/* Force quick and dirty reset */
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WR16(B_HI_CT_REG_COMM_STATE__A, 0),
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@ -126,8 +128,7 @@ u8_t DRXD_HiI2cPatch_1[] =
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};
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/* D0,D1 Version */
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u8_t DRXD_HiI2cPatch_3[] =
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{
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u8_t DRXD_HiI2cPatch_3[] = {
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WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
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0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
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0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
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@ -173,18 +174,21 @@ u8_t DRXD_HiI2cPatch_3[] =
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0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
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0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
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(u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
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/* Force quick and dirty reset */
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WR16(B_HI_CT_REG_COMM_STATE__A, 0),
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END_OF_TABLE
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};
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u8_t DRXD_ResetCEFR[] =
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{
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u8_t DRXD_ResetCEFR[] = {
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WRBLOCK(CE_REG_FR_TREAL00__A, 57),
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0x52, 0x00, /* CE_REG_FR_TREAL00__A */
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0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
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@ -251,9 +255,7 @@ u8_t DRXD_ResetCEFR[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitFEA2_1[] =
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{
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u8_t DRXD_InitFEA2_1[] = {
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WRBLOCK(FE_AD_REG_PD__A, 3),
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0x00, 0x00, /* FE_AD_REG_PD__A */
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0x01, 0x00, /* FE_AD_REG_INVEXT__A */
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@ -339,8 +341,7 @@ u8_t DRXD_InitFEA2_1[] =
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/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
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/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
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u8_t DRXD_InitFEA2_2[] =
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{
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u8_t DRXD_InitFEA2_2[] = {
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WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
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WR16(FE_AG_REG_FGM_WRI__A, 48),
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/* Activate measurement, activate scale */
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@ -358,8 +359,7 @@ u8_t DRXD_InitFEA2_2[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitFEB1_1[] =
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{
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u8_t DRXD_InitFEB1_1[] = {
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WR16(B_FE_AD_REG_PD__A, 0x0000),
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WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
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WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
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@ -373,6 +373,7 @@ u8_t DRXD_InitFEB1_1[] =
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WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
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END_OF_TABLE
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};
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/* with PGA */
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/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
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/* without PGA */
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@ -381,8 +382,7 @@ u8_t DRXD_InitFEB1_1[] =
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/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
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/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
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u8_t DRXD_InitFEB1_2[] =
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{
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u8_t DRXD_InitFEB1_2[] = {
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WR16(B_FE_COMM_EXEC__A, 0x0001),
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/* RF-AGC setup */
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@ -404,8 +404,7 @@ u8_t DRXD_InitFEB1_2[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitCPA2[] =
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{
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u8_t DRXD_InitCPA2[] = {
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WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
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0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
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0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
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@ -435,16 +434,13 @@ u8_t DRXD_InitCPA2[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitCPB1[] =
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{
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u8_t DRXD_InitCPB1[] = {
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WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
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WR16(B_CP_COMM_EXEC__A, 0x0001),
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END_OF_TABLE
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};
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u8_t DRXD_InitCEA2[] =
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{
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u8_t DRXD_InitCEA2[] = {
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WRBLOCK(CE_REG_AVG_POW__A, 4),
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0x62, 0x00, /* CE_REG_AVG_POW__A */
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0x78, 0x00, /* CE_REG_MAX_POW__A */
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@ -482,22 +478,19 @@ u8_t DRXD_InitCEA2[] =
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0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
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0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
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WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
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END_OF_TABLE
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};
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u8_t DRXD_InitCEB1[] =
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{
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u8_t DRXD_InitCEB1[] = {
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WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
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WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
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END_OF_TABLE
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};
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u8_t DRXD_InitEQA2[] =
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{
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u8_t DRXD_InitEQA2[] = {
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WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
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0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
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0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
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@ -512,14 +505,12 @@ u8_t DRXD_InitEQA2[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitEQB1[] =
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{
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u8_t DRXD_InitEQB1[] = {
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WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
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END_OF_TABLE
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};
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u8_t DRXD_ResetECRAM[] =
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{
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u8_t DRXD_ResetECRAM[] = {
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/* Reset packet sync bytes in EC_VD ram */
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WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
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WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
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@ -539,8 +530,7 @@ u8_t DRXD_ResetECRAM[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitECA2[] =
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{
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u8_t DRXD_InitECA2[] = {
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WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
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0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
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0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
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@ -626,8 +616,7 @@ u8_t DRXD_InitECA2[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitECB1[] =
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{
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u8_t DRXD_InitECB1[] = {
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WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
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WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
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WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
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@ -682,8 +671,7 @@ u8_t DRXD_InitECB1[] =
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END_OF_TABLE
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};
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u8_t DRXD_ResetECA2[] =
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{
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u8_t DRXD_ResetECA2[] = {
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WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
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WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
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@ -754,8 +742,7 @@ u8_t DRXD_ResetECA2[] =
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END_OF_TABLE
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};
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u8_t DRXD_InitSC[] =
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{
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u8_t DRXD_InitSC[] = {
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WR16(SC_COMM_EXEC__A, 0),
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WR16(SC_COMM_STATE__A, 0),
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@ -769,8 +756,7 @@ u8_t DRXD_InitSC[] =
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/* Diversity settings */
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u8_t DRXD_InitDiversityFront[] =
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{
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u8_t DRXD_InitDiversityFront[] = {
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/* Start demod ********* RF in , diversity out **************************** */
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WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
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B_SC_RA_RAM_CONFIG_FREQSCAN__M),
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@ -800,17 +786,14 @@ u8_t DRXD_InitDiversityFront[] =
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WR16(B_CC_REG_DIVERSITY__A, 0x0001),
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WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
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WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
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B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |
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B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
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B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
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/* 0x2a ), *//* CE to PASS mux */
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END_OF_TABLE
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};
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u8_t DRXD_InitDiversityEnd[] =
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{
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u8_t DRXD_InitDiversityEnd[] = {
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/* End demod *********** combining RF in and diversity in, MPEG TS out **** */
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/* disable near/far; switch on timing slave mode */
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WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
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@ -852,23 +835,34 @@ u8_t DRXD_InitDiversityEnd[] =
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END_OF_TABLE
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};
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u8_t DRXD_DisableDiversity[] =
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{
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u8_t DRXD_DisableDiversity[] = {
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WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
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WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
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WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ),
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WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ),
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WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ),
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WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ),
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WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ),
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WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ),
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WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
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B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
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WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
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B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
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WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
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B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
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WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
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B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
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WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
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B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
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WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
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B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
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WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ),
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WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ),
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WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ),
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WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ),
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WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ),
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WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ),
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WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
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B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
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WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
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B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
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WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
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B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
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WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
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B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
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WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
|
||||
B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
|
||||
WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
|
||||
B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
|
||||
|
||||
WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
|
||||
WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
|
||||
|
|
@ -876,31 +870,27 @@ u8_t DRXD_DisableDiversity[] =
|
|||
WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
|
||||
WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
|
||||
|
||||
|
||||
WR16(B_CC_REG_DIVERSITY__A, 0x0000),
|
||||
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
|
||||
|
||||
END_OF_TABLE
|
||||
};
|
||||
|
||||
u8_t DRXD_StartDiversityFront[] =
|
||||
{
|
||||
u8_t DRXD_StartDiversityFront[] = {
|
||||
/* Start demod, RF in and diversity out, no combining */
|
||||
WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
|
||||
WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
|
||||
WR16(B_FE_AD_REG_INVEXT__A, 0x0),
|
||||
WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
|
||||
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
|
||||
B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |
|
||||
B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
|
||||
B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
|
||||
|
||||
WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
|
||||
|
||||
END_OF_TABLE
|
||||
};
|
||||
|
||||
u8_t DRXD_StartDiversityEnd[] =
|
||||
{
|
||||
u8_t DRXD_StartDiversityEnd[] = {
|
||||
/* End demod, combining RF in and diversity in, MPEG TS out */
|
||||
WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
|
||||
WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
|
||||
|
|
@ -908,14 +898,12 @@ u8_t DRXD_StartDiversityEnd[] =
|
|||
|
||||
WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
|
||||
B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
|
||||
B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
|
||||
B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ),
|
||||
B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
|
||||
|
||||
END_OF_TABLE
|
||||
};
|
||||
|
||||
u8_t DRXD_DiversityDelay8MHZ[] =
|
||||
{
|
||||
u8_t DRXD_DiversityDelay8MHZ[] = {
|
||||
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
|
||||
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
|
||||
WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@ typedef unsigned long u32_t;
|
|||
|
||||
#define DRXD_SCAN_TIMEOUT (650)
|
||||
|
||||
|
||||
#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
|
||||
#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
|
||||
#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
|
||||
|
|
@ -78,7 +77,6 @@ typedef unsigned long u32_t;
|
|||
#define DIFF_TARGET (4)
|
||||
#define DIFF_MARGIN (1)
|
||||
|
||||
|
||||
extern u8_t DRXD_InitAtomicRead[];
|
||||
extern u8_t DRXD_HiI2cPatch_1[];
|
||||
extern u8_t DRXD_HiI2cPatch_3[];
|
||||
|
|
|
|||
|
|
@ -62,7 +62,6 @@
|
|||
#define DRX_LOCK_FEC 2
|
||||
#define DRX_LOCK_DEMOD 4
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
enum CSCDState {
|
||||
|
|
@ -205,7 +204,6 @@ struct drxd_state {
|
|||
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/* I2C **********************************************************************/
|
||||
/****************************************************************************/
|
||||
|
|
@ -225,7 +223,8 @@ static int i2c_read(struct i2c_adapter *adap,
|
|||
struct i2c_msg msgs[2] = { {.addr = adr,.flags = 0,
|
||||
.buf = msg,.len = len},
|
||||
{.addr = adr,.flags = I2C_M_RD,
|
||||
.buf=answ, .len=alen } };
|
||||
.buf = answ,.len = alen}
|
||||
};
|
||||
if (i2c_transfer(adap, msgs, 2) != 2)
|
||||
return -1;
|
||||
return 0;
|
||||
|
|
@ -245,7 +244,8 @@ static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
|
|||
{
|
||||
u8 adr = state->config.demod_address;
|
||||
u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
|
||||
flags|((reg>>24)&0xff), (reg>>8)&0xff};
|
||||
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
|
||||
};
|
||||
u8 mm2[2];
|
||||
if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
|
||||
return -1;
|
||||
|
|
@ -258,13 +258,15 @@ static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
|
|||
{
|
||||
u8 adr = state->config.demod_address;
|
||||
u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
|
||||
flags|((reg>>24)&0xff), (reg>>8)&0xff};
|
||||
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
|
||||
};
|
||||
u8 mm2[4];
|
||||
|
||||
if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
|
||||
return -1;
|
||||
if (data)
|
||||
*data=mm2[0]|(mm2[1]<<8)|(mm2[2]<<16)|(mm2[3]<<24);
|
||||
*data =
|
||||
mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -273,7 +275,8 @@ static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
|
|||
u8 adr = state->config.demod_address;
|
||||
u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
|
||||
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
|
||||
data&0xff, (data>>8)&0xff };
|
||||
data & 0xff, (data >> 8) & 0xff
|
||||
};
|
||||
|
||||
if (i2c_write(state->i2c, adr, mm, 6) < 0)
|
||||
return -1;
|
||||
|
|
@ -286,7 +289,8 @@ static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
|
|||
u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
|
||||
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
|
||||
data & 0xff, (data >> 8) & 0xff,
|
||||
(data>>16)&0xff, (data>>24)&0xff };
|
||||
(data >> 16) & 0xff, (data >> 24) & 0xff
|
||||
};
|
||||
|
||||
if (i2c_write(state->i2c, adr, mm, 8) < 0)
|
||||
return -1;
|
||||
|
|
@ -298,7 +302,8 @@ static int write_chunk(struct drxd_state *state,
|
|||
{
|
||||
u8 adr = state->config.demod_address;
|
||||
u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
|
||||
flags|((reg>>24)&0xff), (reg>>8)&0xff };
|
||||
flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
|
||||
};
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
|
|
@ -351,7 +356,6 @@ static int WriteTable(struct drxd_state *state, u8 *pTable)
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
|
|
@ -513,8 +517,7 @@ static int DRX_GetLockStatus(struct drxd_state *state, u32 *pLockStatus)
|
|||
|
||||
status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
|
||||
if (status < 0) {
|
||||
printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n",
|
||||
status);
|
||||
printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
@ -550,10 +553,8 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
|
||||
CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
|
||||
&FeAgRegAgModeLop, 0));
|
||||
FeAgRegAgModeLop &=
|
||||
(~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
|
||||
FeAgRegAgModeLop |=
|
||||
FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
|
||||
FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
|
||||
FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
|
||||
CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
|
||||
FeAgRegAgModeLop, 0));
|
||||
|
||||
|
|
@ -579,8 +580,7 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
|
||||
CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A,
|
||||
&FeAgRegAgModeLop, 0));
|
||||
FeAgRegAgModeLop &=
|
||||
(~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
|
||||
FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
|
||||
FeAgRegAgModeLop |=
|
||||
FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
|
||||
CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
|
||||
|
|
@ -613,7 +613,8 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
17, 18, 18, 19,
|
||||
20, 21, 22, 23,
|
||||
24, 26, 27, 28,
|
||||
29, 31};
|
||||
29, 31
|
||||
};
|
||||
|
||||
u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
|
||||
(maxRur + 1);
|
||||
|
|
@ -624,8 +625,7 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
u16 invRurCount = (u16) (cfg->speed /
|
||||
fineSteps);
|
||||
u16 rurCount;
|
||||
if ( invRurCount > maxRur )
|
||||
{
|
||||
if (invRurCount > maxRur) {
|
||||
rurCount = 0;
|
||||
fineSpeed += fineSteps;
|
||||
} else {
|
||||
|
|
@ -644,8 +644,10 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
fastIncrDecLUT[fineSpeed /
|
||||
((fineSteps /
|
||||
(14 + 1)) + 1)];
|
||||
u16 slowIncrDec = slowIncrDecLUT[
|
||||
fineSpeed/(fineSteps/(3+1)) ];
|
||||
u16 slowIncrDec =
|
||||
slowIncrDecLUT[fineSpeed /
|
||||
(fineSteps /
|
||||
(3 + 1))];
|
||||
|
||||
CHK_ERROR(Write16(state,
|
||||
FE_AG_REG_EGC_RUR_CNT__A,
|
||||
|
|
@ -673,7 +675,6 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
||||
{
|
||||
int status = 0;
|
||||
|
|
@ -695,8 +696,7 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
/*==== Mode ====*/
|
||||
|
||||
/* Powerdown PD2, WRI source */
|
||||
state->m_FeAgRegAgPwd &=
|
||||
~(FE_AG_REG_AG_PWD_PWD_PD2__M);
|
||||
state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
|
||||
state->m_FeAgRegAgPwd |=
|
||||
FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
|
||||
CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A,
|
||||
|
|
@ -711,7 +711,6 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
|
|||
CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A,
|
||||
AgModeLop, 0x0000));
|
||||
|
||||
|
||||
/* enable AGC2 pin */
|
||||
{
|
||||
u16 FeAgRegAgAgcSio = 0;
|
||||
|
|
@ -891,23 +890,29 @@ static int DownloadMicrocode(struct drxd_state *state,
|
|||
|
||||
pSrc = (u8 *) pMCImage;
|
||||
Flags = (pSrc[0] << 8) | pSrc[1];
|
||||
pSrc += sizeof(u16); offset += sizeof(u16);
|
||||
pSrc += sizeof(u16);
|
||||
offset += sizeof(u16);
|
||||
nBlocks = (pSrc[0] << 8) | pSrc[1];
|
||||
pSrc += sizeof(u16); offset += sizeof(u16);
|
||||
pSrc += sizeof(u16);
|
||||
offset += sizeof(u16);
|
||||
|
||||
for (i = 0; i < nBlocks; i++) {
|
||||
Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
|
||||
(pSrc[2] << 8) | pSrc[3];
|
||||
pSrc += sizeof(u32); offset += sizeof(u32);
|
||||
pSrc += sizeof(u32);
|
||||
offset += sizeof(u32);
|
||||
|
||||
BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
|
||||
pSrc += sizeof(u16); offset += sizeof(u16);
|
||||
pSrc += sizeof(u16);
|
||||
offset += sizeof(u16);
|
||||
|
||||
Flags = (pSrc[0] << 8) | pSrc[1];
|
||||
pSrc += sizeof(u16); offset += sizeof(u16);
|
||||
pSrc += sizeof(u16);
|
||||
offset += sizeof(u16);
|
||||
|
||||
BlockCRC = (pSrc[0] << 8) | pSrc[1];
|
||||
pSrc += sizeof(u16); offset += sizeof(u16);
|
||||
pSrc += sizeof(u16);
|
||||
offset += sizeof(u16);
|
||||
|
||||
status = WriteBlock(state, Address, BlockSize,
|
||||
pSrc, DRX_I2C_CLEARCRC);
|
||||
|
|
@ -948,16 +953,13 @@ static int HI_CfgCommand(struct drxd_state *state)
|
|||
int status = 0;
|
||||
|
||||
down(&state->mutex);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A,
|
||||
HI_RA_RAM_SRV_RST_KEY_ACT, 0);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_BDL__A,
|
||||
state->hi_cfg_bridge_delay, 0);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
|
||||
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A,
|
||||
HI_RA_RAM_SRV_RST_KEY_ACT, 0);
|
||||
Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
|
||||
|
||||
if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
|
||||
HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
|
||||
|
|
@ -991,8 +993,7 @@ static int HI_ResetCommand(struct drxd_state *state)
|
|||
return status;
|
||||
}
|
||||
|
||||
static int DRX_ConfigureI2CBridge(struct drxd_state *state,
|
||||
int bEnableBridge)
|
||||
static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
|
||||
{
|
||||
state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
|
||||
if (bEnableBridge)
|
||||
|
|
@ -1066,8 +1067,7 @@ static int AtomicReadReg32(struct drxd_state *state,
|
|||
status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
|
||||
*pData = (((u32) buf[0]) << 0) +
|
||||
(((u32) buf[1]) << 8) +
|
||||
(((u32) buf[2]) << 16) +
|
||||
(((u32) buf[3]) << 24);
|
||||
(((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1126,7 +1126,6 @@ static int ResetECOD(struct drxd_state *state)
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
/* Configure PGA switch */
|
||||
|
||||
static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
|
||||
|
|
@ -1192,31 +1191,33 @@ static int InitFE(struct drxd_state *state)
|
|||
{
|
||||
int status;
|
||||
|
||||
do
|
||||
{
|
||||
do {
|
||||
CHK_ERROR(WriteTable(state, state->m_InitFE_1));
|
||||
|
||||
if (state->type_A) {
|
||||
status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
|
||||
FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0);
|
||||
FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
|
||||
0);
|
||||
} else {
|
||||
if (state->PGA)
|
||||
status = SetCfgPga(state, 0);
|
||||
else
|
||||
status =
|
||||
Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
|
||||
B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0);
|
||||
B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
|
||||
0);
|
||||
}
|
||||
|
||||
if (status<0) break;
|
||||
if (status < 0)
|
||||
break;
|
||||
CHK_ERROR(Write16(state, FE_AG_REG_AG_AGC_SIO__A,
|
||||
state->m_FeAgRegAgAgcSio, 0x0000));
|
||||
CHK_ERROR( Write16( state, FE_AG_REG_AG_PWD__A,state->m_FeAgRegAgPwd,
|
||||
CHK_ERROR(Write16
|
||||
(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd,
|
||||
0x0000));
|
||||
|
||||
CHK_ERROR(WriteTable(state, state->m_InitFE_2));
|
||||
|
||||
|
||||
} while (0);
|
||||
|
||||
return status;
|
||||
|
|
@ -1236,8 +1237,7 @@ static int SC_WaitForReady(struct drxd_state *state)
|
|||
u16 curCmd;
|
||||
int i;
|
||||
|
||||
for(i = 0; i < DRXD_MAX_RETRIES; i += 1 )
|
||||
{
|
||||
for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
|
||||
int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
|
||||
if (status == 0 || curCmd == 0)
|
||||
return status;
|
||||
|
|
@ -1255,8 +1255,7 @@ static int SC_SendCommand(struct drxd_state *state, u16 cmd)
|
|||
|
||||
Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
|
||||
|
||||
if( errCode == 0xFFFF )
|
||||
{
|
||||
if (errCode == 0xFFFF) {
|
||||
printk("Command Error\n");
|
||||
status = -1;
|
||||
}
|
||||
|
|
@ -1288,7 +1287,6 @@ static int SC_ProcStartCommand(struct drxd_state *state,
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
static int SC_SetPrefParamCommand(struct drxd_state *state,
|
||||
u16 subCmd, u16 param0, u16 param1)
|
||||
{
|
||||
|
|
@ -1301,8 +1299,7 @@ static int SC_SetPrefParamCommand(struct drxd_state *state,
|
|||
CHK_ERROR(Write16(state, SC_RA_RAM_PARAM1__A, param1, 0));
|
||||
CHK_ERROR(Write16(state, SC_RA_RAM_PARAM0__A, param0, 0));
|
||||
|
||||
CHK_ERROR( SC_SendCommand(state,
|
||||
SC_RA_RAM_CMD_SET_PREF_PARAM) );
|
||||
CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM));
|
||||
} while (0);
|
||||
up(&state->mutex);
|
||||
return status;
|
||||
|
|
@ -1316,8 +1313,7 @@ static int SC_GetOpParamCommand(struct drxd_state *state, u16 *result)
|
|||
down(&state->mutex);
|
||||
do {
|
||||
CHK_ERROR(SC_WaitForReady(state));
|
||||
CHK_ERROR( SC_SendCommand(state,
|
||||
SC_RA_RAM_CMD_GET_OP_PARAM) );
|
||||
CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM));
|
||||
CHK_ERROR(Read16(state, SC_RA_RAM_PARAM0__A, result, 0));
|
||||
} while (0);
|
||||
up(&state->mutex);
|
||||
|
|
@ -1338,31 +1334,24 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
|
|||
/*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A,
|
||||
&EcOcRegOcModeLop, 0)); */
|
||||
|
||||
if( state->operation_mode == OM_DVBT_Diversity_Front )
|
||||
{
|
||||
if ( bEnableOutput )
|
||||
{
|
||||
if (state->operation_mode == OM_DVBT_Diversity_Front) {
|
||||
if (bEnableOutput) {
|
||||
EcOcRegOcModeHip |=
|
||||
B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
|
||||
}
|
||||
else
|
||||
} else
|
||||
EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
|
||||
EcOcRegOcModeLop |=
|
||||
EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
|
||||
|
||||
if (bEnableOutput)
|
||||
EcOcRegOcMpgSio &=
|
||||
(~(EC_OC_REG_OC_MPG_SIO__M));
|
||||
EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
|
||||
else
|
||||
EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
|
||||
|
||||
/* Don't Insert RS Byte */
|
||||
if( state->insert_rs_byte )
|
||||
{
|
||||
if (state->insert_rs_byte) {
|
||||
EcOcRegOcModeLop &=
|
||||
(~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
|
||||
EcOcRegOcModeHip &=
|
||||
|
|
@ -1525,21 +1514,17 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
|
|||
causes trouble (at least for diversity */
|
||||
CHK_ERROR(Read32(state, LC_RA_RAM_IFINCR_NOM_L__A,
|
||||
((u32 *) & nomincr), 0));
|
||||
CHK_ERROR( Read32(state, FE_IF_REG_INCR0__A,
|
||||
(u32 *) &incr,0 ));
|
||||
CHK_ERROR(Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0));
|
||||
|
||||
if (state->type_A) {
|
||||
if( (nomincr - incr < -500) ||
|
||||
(nomincr - incr > 500 ) )
|
||||
if ((nomincr - incr < -500) || (nomincr - incr > 500))
|
||||
break;
|
||||
} else {
|
||||
if( (nomincr - incr < -2000 ) ||
|
||||
(nomincr - incr > 2000 ) )
|
||||
if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
|
||||
break;
|
||||
}
|
||||
|
||||
switch( state->param.u.ofdm.bandwidth )
|
||||
{
|
||||
switch (state->param.u.ofdm.bandwidth) {
|
||||
case BANDWIDTH_8_MHZ:
|
||||
bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
|
||||
break;
|
||||
|
|
@ -1560,27 +1545,27 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
|
|||
sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
|
||||
sysClockFreq = (u32) (sysClockInHz / 1000);
|
||||
/* rounding */
|
||||
if ( ( sysClockInHz%1000 ) > 500 )
|
||||
{
|
||||
if ((sysClockInHz % 1000) > 500) {
|
||||
sysClockFreq++;
|
||||
}
|
||||
|
||||
/* Compute clock deviation in ppm */
|
||||
oscClockDeviation = (u16) (
|
||||
(((s32)(sysClockFreq) -
|
||||
(s32)(state->expected_sys_clock_freq))*
|
||||
1000000L)/(s32)(state->expected_sys_clock_freq) );
|
||||
oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
|
||||
(s32)
|
||||
(state->expected_sys_clock_freq)) *
|
||||
1000000L) /
|
||||
(s32)
|
||||
(state->expected_sys_clock_freq));
|
||||
|
||||
Diff = oscClockDeviation - state->osc_clock_deviation;
|
||||
/*printk("sysclockdiff=%d\n", Diff); */
|
||||
if (Diff >= -200 && Diff <= 200) {
|
||||
state->sys_clock_freq = (u16) sysClockFreq;
|
||||
if( oscClockDeviation !=
|
||||
state->osc_clock_deviation ) {
|
||||
if (oscClockDeviation != state->osc_clock_deviation) {
|
||||
if (state->config.osc_deviation) {
|
||||
state->config.osc_deviation(
|
||||
state->priv,
|
||||
oscClockDeviation, 1);
|
||||
state->config.osc_deviation(state->priv,
|
||||
oscClockDeviation,
|
||||
1);
|
||||
state->osc_clock_deviation =
|
||||
oscClockDeviation;
|
||||
}
|
||||
|
|
@ -1649,15 +1634,13 @@ static int DRX_Stop(struct drxd_state *state)
|
|||
B_EQ_COMM_EXEC__A,
|
||||
SC_COMM_EXEC_CTL_STOP, 0));
|
||||
CHK_ERROR(Write16(state,
|
||||
EC_OD_REG_COMM_EXEC__A,
|
||||
0x0000, 0 ));
|
||||
EC_OD_REG_COMM_EXEC__A, 0x0000, 0));
|
||||
}
|
||||
|
||||
} while (0);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
int SetOperationMode(struct drxd_state *state, int oMode)
|
||||
{
|
||||
int status;
|
||||
|
|
@ -1678,15 +1661,12 @@ int SetOperationMode(struct drxd_state *state, int oMode)
|
|||
break;
|
||||
}
|
||||
|
||||
switch(oMode)
|
||||
{
|
||||
switch (oMode) {
|
||||
case OM_DVBT_Diversity_Front:
|
||||
status = WriteTable(state,
|
||||
state->m_InitDiversityFront);
|
||||
status = WriteTable(state, state->m_InitDiversityFront);
|
||||
break;
|
||||
case OM_DVBT_Diversity_End:
|
||||
status = WriteTable(state,
|
||||
state->m_InitDiversityEnd);
|
||||
status = WriteTable(state, state->m_InitDiversityEnd);
|
||||
break;
|
||||
case OM_Default:
|
||||
/* We need to check how to
|
||||
|
|
@ -1702,8 +1682,6 @@ int SetOperationMode(struct drxd_state *state, int oMode)
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int StartDiversity(struct drxd_state *state)
|
||||
{
|
||||
int status = 0;
|
||||
|
|
@ -1716,15 +1694,12 @@ static int StartDiversity(struct drxd_state *state)
|
|||
} else if (state->operation_mode == OM_DVBT_Diversity_End) {
|
||||
CHK_ERROR(WriteTable(state,
|
||||
state->m_StartDiversityEnd));
|
||||
if( state->param.u.ofdm.bandwidth ==
|
||||
BANDWIDTH_8_MHZ ) {
|
||||
CHK_ERROR(
|
||||
WriteTable(state,
|
||||
if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
|
||||
CHK_ERROR(WriteTable(state,
|
||||
state->
|
||||
m_DiversityDelay8MHZ));
|
||||
} else {
|
||||
CHK_ERROR(
|
||||
WriteTable(state,
|
||||
CHK_ERROR(WriteTable(state,
|
||||
state->
|
||||
m_DiversityDelay6MHZ));
|
||||
}
|
||||
|
|
@ -1746,7 +1721,6 @@ static int StartDiversity(struct drxd_state *state)
|
|||
return status;
|
||||
}
|
||||
|
||||
|
||||
static int SetFrequencyShift(struct drxd_state *state,
|
||||
u32 offsetFreq, int channelMirrored)
|
||||
{
|
||||
|
|
@ -1768,8 +1742,7 @@ static int SetFrequencyShift(struct drxd_state *state,
|
|||
1 << 28, state->sys_clock_freq);
|
||||
/* Remove integer part */
|
||||
state->fe_fs_add_incr &= 0x0FFFFFFFL;
|
||||
if (negativeShift)
|
||||
{
|
||||
if (negativeShift) {
|
||||
state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
|
||||
}
|
||||
|
||||
|
|
@ -1794,21 +1767,17 @@ static int SetCfgNoiseCalibration (struct drxd_state *state,
|
|||
int status = 0;
|
||||
|
||||
do {
|
||||
CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A,
|
||||
&beOptEna, 0));
|
||||
if (noiseCal->cpOpt)
|
||||
{
|
||||
CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0));
|
||||
if (noiseCal->cpOpt) {
|
||||
beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
|
||||
} else {
|
||||
beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
|
||||
CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A,
|
||||
noiseCal->cpNexpOfs, 0));
|
||||
}
|
||||
CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A,
|
||||
beOptEna, 0));
|
||||
CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0));
|
||||
|
||||
if( !state->type_A )
|
||||
{
|
||||
if (!state->type_A) {
|
||||
CHK_ERROR(Write16(state,
|
||||
B_SC_RA_RAM_CO_TD_CAL_2K__A,
|
||||
noiseCal->tdCal2k, 0));
|
||||
|
|
@ -1902,8 +1871,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
|
|||
break;
|
||||
}
|
||||
|
||||
switch( p->guard_interval )
|
||||
{
|
||||
switch (p->guard_interval) {
|
||||
case GUARD_INTERVAL_1_4:
|
||||
transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
|
||||
break;
|
||||
|
|
@ -1923,8 +1891,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
|
|||
break;
|
||||
}
|
||||
|
||||
switch( p->hierarchy_information )
|
||||
{
|
||||
switch (p->hierarchy_information) {
|
||||
case HIERARCHY_1:
|
||||
transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
|
||||
if (state->type_A) {
|
||||
|
|
@ -2157,8 +2124,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
|
|||
|
||||
}
|
||||
|
||||
switch( p->code_rate_HP )
|
||||
{
|
||||
switch (p->code_rate_HP) {
|
||||
case FEC_1_2:
|
||||
transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
|
||||
if (state->type_A) {
|
||||
|
|
@ -2216,8 +2182,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
|
|||
by SC for fix for some 8K,1/8 guard but is restored by
|
||||
InitEC and ResetEC
|
||||
functions */
|
||||
switch( p->bandwidth )
|
||||
{
|
||||
switch (p->bandwidth) {
|
||||
case BANDWIDTH_AUTO:
|
||||
case BANDWIDTH_8_MHZ:
|
||||
/* (64/7)*(8/8)*1000000 */
|
||||
|
|
@ -2268,8 +2233,7 @@ static int DRX_Start(struct drxd_state *state, s32 off)
|
|||
|
||||
CHK_ERROR(SetCfgNoiseCalibration(state, &state->noise_cal));
|
||||
|
||||
if (state->cscd_state == CSCD_INIT )
|
||||
{
|
||||
if (state->cscd_state == CSCD_INIT) {
|
||||
/* switch on SRMM scan in SC */
|
||||
CHK_ERROR(Write16(state,
|
||||
SC_RA_RAM_SAMPLE_RATE_COUNT__A,
|
||||
|
|
@ -2279,7 +2243,6 @@ static int DRX_Start(struct drxd_state *state, s32 off)
|
|||
state->cscd_state = CSCD_SET;
|
||||
}
|
||||
|
||||
|
||||
/* Now compute FE_IF_REG_INCR */
|
||||
/*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
|
||||
((SysFreq / BandWidth) * (2^21) ) - (2^23) */
|
||||
|
|
@ -2370,8 +2333,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
|
|||
state->if_agc_cfg.maxOutputLevel = 1023;
|
||||
state->if_agc_cfg.speed = 904;
|
||||
|
||||
if( ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX )
|
||||
{
|
||||
if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
|
||||
state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
|
||||
state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
|
||||
}
|
||||
|
|
@ -2380,9 +2342,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
|
|||
ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
|
||||
ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
|
||||
ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
|
||||
ulIfAgcSpeed <= DRXD_FE_CTRL_MAX
|
||||
)
|
||||
{
|
||||
ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
|
||||
state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
|
||||
state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
|
||||
state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
|
||||
|
|
@ -2409,9 +2369,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
|
|||
ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
|
||||
ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
|
||||
ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
|
||||
ulRfAgcSpeed <= DRXD_FE_CTRL_MAX
|
||||
)
|
||||
{
|
||||
ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
|
||||
state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
|
||||
state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
|
||||
state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
|
||||
|
|
@ -2419,8 +2377,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
|
|||
state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
|
||||
}
|
||||
|
||||
if( ulRfAgcMode == 2 )
|
||||
{
|
||||
if (ulRfAgcMode == 2) {
|
||||
state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
|
||||
}
|
||||
|
||||
|
|
@ -2431,8 +2388,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
|
|||
state->app_env_diversity = (enum app_env)
|
||||
(ulEnvironmentDiversity);
|
||||
|
||||
if( ulIFFilter == IFFILTER_DISCRETE )
|
||||
{
|
||||
if (ulIFFilter == IFFILTER_DISCRETE) {
|
||||
/* discrete filter */
|
||||
state->noise_cal.cpOpt = 0;
|
||||
state->noise_cal.cpNexpOfs = 40;
|
||||
|
|
@ -2448,10 +2404,13 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
|
|||
state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
|
||||
|
||||
state->chip_adr = (state->config.demod_address << 1) | 1;
|
||||
switch( ulHiI2cPatch )
|
||||
{
|
||||
case 1 : state->m_HiI2cPatch = DRXD_HiI2cPatch_1; break;
|
||||
case 3 : state->m_HiI2cPatch = DRXD_HiI2cPatch_3; break;
|
||||
switch (ulHiI2cPatch) {
|
||||
case 1:
|
||||
state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
|
||||
break;
|
||||
case 3:
|
||||
state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
|
||||
break;
|
||||
default:
|
||||
state->m_HiI2cPatch = NULL;
|
||||
}
|
||||
|
|
@ -2525,8 +2484,7 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
|
|||
|
||||
if (state->config.osc_deviation)
|
||||
state->osc_clock_deviation =
|
||||
state->config.osc_deviation(state->priv,
|
||||
0, 0);
|
||||
state->config.osc_deviation(state->priv, 0, 0);
|
||||
{
|
||||
/* Handle clock deviation */
|
||||
s32 devB;
|
||||
|
|
@ -2539,14 +2497,13 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
|
|||
devB = (2);
|
||||
else
|
||||
devB = (-2);
|
||||
if ( (devB*(devA%1000000L)>1000000L ) )
|
||||
{
|
||||
if ((devB * (devA % 1000000L) > 1000000L)) {
|
||||
/* add +1 or -1 */
|
||||
deviation += (devB / 2);
|
||||
}
|
||||
|
||||
state->sys_clock_freq=(u16)((state->
|
||||
expected_sys_clock_freq)+
|
||||
state->sys_clock_freq =
|
||||
(u16) ((state->expected_sys_clock_freq) +
|
||||
deviation);
|
||||
}
|
||||
CHK_ERROR(InitHI(state));
|
||||
|
|
@ -2589,15 +2546,13 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
|
|||
CHK_ERROR(Write16(state, LC_COMM_EXEC__A,
|
||||
SC_COMM_EXEC_CTL_STOP, 0));
|
||||
|
||||
|
||||
driverVersion = (((VERSION_MAJOR / 10) << 4) +
|
||||
(VERSION_MAJOR % 10)) << 24;
|
||||
driverVersion += (((VERSION_MINOR / 10) << 4) +
|
||||
(VERSION_MINOR % 10)) << 16;
|
||||
driverVersion += ((VERSION_PATCH / 1000) << 12) +
|
||||
((VERSION_PATCH / 100) << 8) +
|
||||
((VERSION_PATCH/10 )<< 4) +
|
||||
(VERSION_PATCH%10 );
|
||||
((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
|
||||
|
||||
CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX,
|
||||
driverVersion, 0));
|
||||
|
|
@ -2629,8 +2584,7 @@ int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
|
|||
/****************************************************************************/
|
||||
/****************************************************************************/
|
||||
|
||||
static int drxd_read_signal_strength(struct dvb_frontend *fe,
|
||||
u16 *strength)
|
||||
static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
|
||||
{
|
||||
struct drxd_state *state = fe->demodulator_priv;
|
||||
u32 value;
|
||||
|
|
@ -2644,7 +2598,6 @@ static int drxd_read_signal_strength(struct dvb_frontend *fe,
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
|
||||
{
|
||||
struct drxd_state *state = fe->demodulator_priv;
|
||||
|
|
@ -2756,8 +2709,7 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
|
|||
if (state->config.pll_set &&
|
||||
state->config.pll_set(state->priv, param,
|
||||
state->config.pll_address,
|
||||
state->config.demoda_address,
|
||||
&off)<0) {
|
||||
state->config.demoda_address, &off) < 0) {
|
||||
printk("Error in pll_set\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -2767,7 +2719,6 @@ static int drxd_set_frontend(struct dvb_frontend *fe,
|
|||
return DRX_Start(state, off);
|
||||
}
|
||||
|
||||
|
||||
static void drxd_release(struct dvb_frontend *fe)
|
||||
{
|
||||
struct drxd_state *state = fe->demodulator_priv;
|
||||
|
|
@ -2791,9 +2742,7 @@ static struct dvb_frontend_ops drxd_ops = {
|
|||
FE_CAN_QAM_AUTO |
|
||||
FE_CAN_TRANSMISSION_MODE_AUTO |
|
||||
FE_CAN_GUARD_INTERVAL_AUTO |
|
||||
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
|
||||
FE_CAN_MUTE_TS
|
||||
},
|
||||
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
|
||||
|
||||
.release = drxd_release,
|
||||
.init = drxd_init,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Add table
Reference in a new issue