usb: phy: qmp: Remove QMP PHY revision based phy_reg_offset
This change removes QMP PHY revision based phy_reg_offset from QMP PHY driver. It makes mandatory to have required QMP PHY related register offset through devicetree. It also removes different revision ID related register offset usage and requirement. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
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2 changed files with 12 additions and 57 deletions
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@ -110,6 +110,14 @@ Required properties:
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microvolts or a value corresponding to voltage corner
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- qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg offset, its
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value, delay after register write. It is not must property to have for emulation.
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- qcom,qmp-phy-reg-offset: Provides important phy register offsets in an order
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defined in the phy driver. Provide below mentioned register offsets in order:
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USB3_PHY_PCS_STATUS,
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USB3_PHY_AUTONOMOUS_MODE_CTRL,
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USB3_PHY_LFPS_RXTERM_IRQ_CLEAR,
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USB3_PHY_POWER_DOWN_CONTROL,
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USB3_PHY_SW_RESET,
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USB3_PHY_START
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Optional properties:
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- reg: Additional register set of address and length to control QMP PHY
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@ -117,8 +125,6 @@ Optional properties:
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the USB PHY and the controller must rely on external VBUS notification in
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order to manually relay the notification to the SSPHY.
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- qcom,emulation: Indicates that we are running on emulation platform.
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- qcom,qmp-phy-reg-offset: If present stores phy register offsets in an order
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defined in the phy driver.
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Example:
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ssphy0: ssphy@f9b38000 {
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@ -42,10 +42,6 @@
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#define ARCVR_DTCT_EVENT_SEL BIT(4)
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enum qmp_phy_rev_reg {
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USB3_REVISION_ID0,
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USB3_REVISION_ID1,
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USB3_REVISION_ID2,
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USB3_REVISION_ID3,
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USB3_PHY_PCS_STATUS,
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USB3_PHY_AUTONOMOUS_MODE_CTRL,
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USB3_PHY_LFPS_RXTERM_IRQ_CLEAR,
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@ -55,34 +51,6 @@ enum qmp_phy_rev_reg {
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USB3_PHY_REG_MAX,
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};
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/* QMP PHY register offset for rev1 */
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unsigned int qmp_phy_rev1[] = {
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[USB3_REVISION_ID0] = 0x730,
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[USB3_REVISION_ID1] = 0x734,
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[USB3_REVISION_ID2] = 0x738,
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[USB3_REVISION_ID3] = 0x73c,
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[USB3_PHY_PCS_STATUS] = 0x728,
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[USB3_PHY_AUTONOMOUS_MODE_CTRL] = 0x6BC,
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[USB3_PHY_LFPS_RXTERM_IRQ_CLEAR] = 0x6C0,
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[USB3_PHY_POWER_DOWN_CONTROL] = 0x604,
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[USB3_PHY_SW_RESET] = 0x600,
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[USB3_PHY_START] = 0x608,
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};
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/* QMP PHY register offset for rev2 */
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unsigned int qmp_phy_rev2[] = {
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[USB3_REVISION_ID0] = 0x788,
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[USB3_REVISION_ID1] = 0x78C,
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[USB3_REVISION_ID2] = 0x790,
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[USB3_REVISION_ID3] = 0x794,
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[USB3_PHY_PCS_STATUS] = 0x77C,
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[USB3_PHY_AUTONOMOUS_MODE_CTRL] = 0x6D4,
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[USB3_PHY_LFPS_RXTERM_IRQ_CLEAR] = 0x6D8,
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[USB3_PHY_POWER_DOWN_CONTROL] = 0x604,
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[USB3_PHY_SW_RESET] = 0x600,
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[USB3_PHY_START] = 0x608,
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};
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/* reg values to write */
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struct qmp_reg_val {
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u32 offset;
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@ -124,11 +92,9 @@ static const struct of_device_id msm_usb_id_table[] = {
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},
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{
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.compatible = "qcom,usb-ssphy-qmp-v1",
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.data = qmp_phy_rev1,
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},
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{
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.compatible = "qcom,usb-ssphy-qmp-v2",
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.data = qmp_phy_rev2,
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},
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{ },
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};
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@ -529,7 +495,6 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct resource *res;
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int ret = 0, size = 0;
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const struct of_device_id *phy_ver;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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@ -604,30 +569,14 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev)
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phy->reg_offset_cnt);
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} else {
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dev_err(dev, "err mem alloc for qmp_phy_reg_offset\n");
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return -ENOMEM;
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}
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}
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phy_ver = of_match_device(msm_usb_id_table, &pdev->dev);
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if (phy_ver) {
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dev_dbg(dev, "Found QMP PHY version as:%s.\n",
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phy_ver->compatible);
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if (phy_ver->data) {
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phy->phy_reg = (unsigned int *)phy_ver->data;
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} else if (phy->qmp_phy_reg_offset) {
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phy->phy_reg = phy->qmp_phy_reg_offset;
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} else {
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dev_err(dev,
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"QMP PHY version match but wrong data val.\n");
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ret = -EINVAL;
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}
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phy->phy_reg = phy->qmp_phy_reg_offset;
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} else {
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dev_err(dev, "QMP PHY version mismatch.\n");
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ret = -ENODEV;
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dev_err(dev, "err provide qcom,qmp-phy-reg-offset\n");
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return -EINVAL;
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}
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if (ret)
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goto err;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"qmp_phy_base");
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if (!res) {
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