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drm/nouveau/gr/gk104-: correct crop/zrop num_active_fbps setting

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-03-26 13:26:20 +10:00
parent 3740c82590
commit 6eb7082621
3 changed files with 11 additions and 14 deletions
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1
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
View file

@ -88,6 +88,7 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_grctx *); void gk104_grctx_generate_pagepool(struct gf100_grctx *);
void gk104_grctx_generate_unkn(struct gf100_gr_priv *); void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *); void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *);
extern struct nvkm_oclass *gk110_grctx_oclass; extern struct nvkm_oclass *gk110_grctx_oclass;
extern struct nvkm_oclass *gk110b_grctx_oclass; extern struct nvkm_oclass *gk110b_grctx_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
View file

@ -940,6 +940,14 @@ gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
nv_wr32(priv, 0x40780c + (i * 4), data[i]); nv_wr32(priv, 0x40780c + (i * 4), data[i]);
} }
void
gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv)
{
const u32 fbp_count = nv_rd32(priv, 0x120074);
nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */
nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void void
gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{ {
@ -970,13 +978,7 @@ gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
if (priv->gpc_nr == 1) { gk104_grctx_generate_rop_active_fbps(priv);
nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
} else {
nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
gf100_gr_icmd(priv, oclass->icmd); gf100_gr_icmd(priv, oclass->icmd);

8
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
View file

@ -982,13 +982,7 @@ gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
if (priv->gpc_nr == 1) { gk104_grctx_generate_rop_active_fbps(priv);
nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
} else {
nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
gf100_gr_icmd(priv, oclass->icmd); gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400); nv_wr32(priv, 0x404154, 0x00000400);