drm/nv50: preserve an unknown SOR_MODECTRL value for DP encoders
This value interacts with some registers we don't currently know how to program properly ourselves. The default of 5 that we were using matches what the VBIOS on early DP cards do, but later ones use 6, which would cause nouveau to program an incorrect mode on these chips. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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d327dd4e77
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2 changed files with 22 additions and 1 deletions
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@ -47,6 +47,7 @@ struct nouveau_encoder {
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union {
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struct {
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int mc_unknown;
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int dpcd_version;
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int link_nr;
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int link_bw;
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@ -211,7 +211,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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mode_ctl = 0x0200;
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break;
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case OUTPUT_DP:
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mode_ctl |= 0x00050000;
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mode_ctl |= (nv_encoder->dp.mc_unknown << 16);
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if (nv_encoder->dcb->sorconf.link & 1)
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mode_ctl |= 0x00000800;
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else
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@ -274,6 +274,7 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = {
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int
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nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_encoder *nv_encoder = NULL;
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struct drm_encoder *encoder;
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bool dum;
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@ -319,5 +320,24 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry)
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encoder->possible_crtcs = entry->heads;
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encoder->possible_clones = 0;
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if (nv_encoder->dcb->type == OUTPUT_DP) {
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uint32_t mc, or = nv_encoder->or;
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if (dev_priv->chipset < 0x90 ||
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dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
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mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or));
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else
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mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or));
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switch ((mc & 0x00000f00) >> 8) {
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case 8:
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case 9:
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nv_encoder->dp.mc_unknown = (mc & 0x000f0000) >> 16;
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break;
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default:
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break;
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}
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}
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return 0;
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}
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