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clk: msm: clock-generic: Fix max_div calculation for 32 bit

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The ULONG_MAX value on 32 bit compilers is +4,294,967,295 and when divided
with some high frequencies, it could lead to min_div > max_div. Thus
resulting in clk_set_rate failure for higher frequencies.

CRs-Fixed: 971371
Change-Id: Id982328aeadf24d29e295e042a57453ea4e35c1b
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2016-02-02 20:25:36 +05:30 • committed by David Keitel
parent 938ef7a4ac
commit 71910a2a13
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/msm/clock-generic.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -267,7 +267,7 @@ static long __div_round_rate(struct div_data *data, unsigned long rate,
rate = max(rate, 1UL);
min_div = max(data->min_div, 1U);
max_div = min(data->max_div, (unsigned int) (ULONG_MAX / rate));
max_div = min(data->max_div, (unsigned int) (ULONG_MAX));
/*
* div values are doubled for half dividers.